From patchwork Wed Sep 25 11:19:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11160451 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 704521709 for ; Wed, 25 Sep 2019 11:19:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4443121D7E for ; Wed, 25 Sep 2019 11:19:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569410397; bh=87PQvrUP9H9IHcIyzFEMvU+vHO6KPy65fWLTapdtfAk=; h=From:To:Cc:Subject:Date:List-ID:From; b=Oyuww7/XdxQebR1mCM/VSkRwiQqjvuWxXlXjulJq00koH/m+bhONe+fBzDc4QWZrc pzDRAfbNWEejPkjwe+djr33TlV6TboSg6YzF7PAUM6gWl3gJf0mbqnwQJY+CTxuLgZ sLDnuHedxD0UR535Fiuv5sWDK2z2dU11HjDnDR3c= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732154AbfIYLT4 (ORCPT ); Wed, 25 Sep 2019 07:19:56 -0400 Received: from foss.arm.com ([217.140.110.172]:46854 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725913AbfIYLT4 (ORCPT ); Wed, 25 Sep 2019 07:19:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 825A71570; Wed, 25 Sep 2019 04:19:55 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 49A813F694; Wed, 25 Sep 2019 04:19:54 -0700 (PDT) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: Will Deacon , Mark Rutland , Catalin Marinas , James Morse , Suzuki K Poulose , Julien Thierry Subject: [PATCH 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Date: Wed, 25 Sep 2019 12:19:36 +0100 Message-Id: <20190925111941.88103-1-maz@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Similarily to erratum 1165522 that affects Cortex-A76, our good old friends A57 and A72 respectively suffer from errata 1319367 and 1319537, potentially resulting in TLB corruption if the CPU speculates an AT instruction while switching guests. The fix is slightly more involved since we don't have VHE to help us here, but the idea is the same: When switching a guest in, we must prevent any speculated AT from being able to parse the page tables until S2 is up and running. Only at this stage can we allow AT to take place. For this, we always restore the guest sysregs first, except for its SCTLR and TCR registers, which must be set with SCTLR.M=1 and TCR.EPD{0,1} = {1, 1}, effectively disabling the PTW and TLB allocation. Once S2 is setup, we restore the guest's SCTLR and TCR. Similar things must be done on TLB invalidation... Fun. This has been tested on an AMD Seattle box. Marc Zyngier (5): arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions arm64: KVM: Reorder system register restoration and stage-2 activation arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context arm64: Enable and document ARM errata 1319367 and 1319537 Documentation/arm64/silicon-errata.rst | 4 +++ arch/arm64/Kconfig | 10 ++++++ arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/kernel/cpu_errata.c | 13 +++++-- arch/arm64/kvm/hyp/switch.c | 48 ++++++++++++++++++++++---- arch/arm64/kvm/hyp/sysreg-sr.c | 14 ++++++-- arch/arm64/kvm/hyp/tlb.c | 23 ++++++++++++ 7 files changed, 103 insertions(+), 12 deletions(-)