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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id c25sm474794ejx.39.2020.12.02.10.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Dec 2020 10:44:17 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Richard Henderson , kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 0/9] target/mips: Simplify MSA TCG logic Date: Wed, 2 Dec 2020 19:44:06 +0100 Message-Id: <20201202184415.1434484-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org I converted MSA opcodes to decodetree. To keep the series small I split it in 2, this is the non-decodetree specific patches (so non-decodetree experts can review it ;) ). First we stop using env->insn_flags to check for MSAi presence, then we restrict TCG functions to DisasContext*. Based-on: <20201130102228.2395100-1-f4bug@amsat.org> "target/mips: Allow executing MSA instructions on Loongson-3A4000" Philippe Mathieu-Daudé (9): target/mips: Introduce ase_msa_available() helper target/mips: Simplify msa_reset() target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA target/mips: Simplify MSA TCG logic target/mips: Remove now unused ASE_MSA definition target/mips: Alias MSA vector registers on FPU scalar registers target/mips: Extract msa_translate_init() from mips_tcg_init() target/mips: Remove CPUMIPSState* argument from gen_msa*() methods target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() target/mips/internal.h | 8 +- target/mips/mips-defs.h | 1 - target/mips/kvm.c | 12 +- target/mips/translate.c | 206 ++++++++++++++++++------------- target/mips/translate_init.c.inc | 12 +- 5 files changed, 138 insertions(+), 101 deletions(-) Reviewed-by: Jiaxun Yang Reviewed-by: Jiaxun Yang