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Thu, 29 Apr 2021 16:29:48 +0000 Received: from SDONTHINENI-DESKTOP.nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 16:29:46 +0000 From: Shanker Donthineni To: Marc Zyngier , Alex Williamson CC: Will Deacon , Catalin Marinas , Christoffer Dall , , , , , Vikram Sethi , Shanker Donthineni , "Jason Sequeira" Subject: [RFC 0/2] [RFC] Honor PCI prefetchable attributes for a virtual machine on ARM64 Date: Thu, 29 Apr 2021 11:29:04 -0500 Message-ID: <20210429162906.32742-1-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2330b376-b545-4e6b-6277-08d90b2c0196 X-MS-TrafficTypeDiagnostic: CY4PR12MB1399: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 16:29:48.0066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2330b376-b545-4e6b-6277-08d90b2c0196 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1399 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Problem statement: Virtual machine crashes when NVIDIA GPU driver access a prefetchable BAR space due to the unaligned reads/writes for pass-through devices. The same binary works fine as expected in the host kernel. Only one BAR has control & status registers (CSR) and other PCI BARs are marked as prefetchable. NVIDIA GPU driver uses the write-combine feature for mapping the prefetchable BARs to improve performance. This problem applies to all other drivers which want to enable WC. Solution: Honor PCI prefetchable attributes for the guest operating systems. Proposal: ARM64-KVM uses VMA struct for the needed information e.g. region physical address, size, and memory-type (struct page backed mapping or anonymous memory) for setting up a stage-2 page table. Right now memory region either can be mapped as DEVICE (strongly ordered) or NORMAL (write-back cache) depends on the flag VM_PFNMAP in VMA. VFIO-PCI will keep the prefetchable (write-combine) information in vma->vm_page_prot similar to other fields, and KVM will prepare stage-2 entries based on the memory-type attribute that was set in VMA. Shanker Donthineni (2): vfio/pci: keep the prefetchable attribute of a BAR region in VMA KVM: arm64: Add write-combine support for stage-2 entries arch/arm64/include/asm/kvm_mmu.h | 3 ++- arch/arm64/include/asm/kvm_pgtable.h | 2 ++ arch/arm64/include/asm/memory.h | 4 +++- arch/arm64/kvm/hyp/pgtable.c | 9 +++++++-- arch/arm64/kvm/mmu.c | 22 +++++++++++++++++++--- arch/arm64/kvm/vgic/vgic-v2.c | 2 +- drivers/vfio/pci/vfio_pci.c | 6 +++++- 7 files changed, 39 insertions(+), 9 deletions(-)