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Tue, 31 Aug 2021 03:07:30 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 Aug 2021 20:07:29 -0700 Received: from Asurada-Nvidia.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 31 Aug 2021 03:07:29 +0000 From: Nicolin Chen To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [RFC][PATCH v2 00/13] iommu/arm-smmu-v3: Add NVIDIA implementation Date: Mon, 30 Aug 2021 19:59:10 -0700 Message-ID: <20210831025923.15812-1-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8c9a6db2-7cb6-499c-410a-08d96c2c78a2 X-MS-TrafficTypeDiagnostic: BL0PR12MB5537: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 03:07:30.6257 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c9a6db2-7cb6-499c-410a-08d96c2c78a2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5537 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The SMMUv3 devices implemented in the Grace SoC support NVIDIA's custom CMDQ-Virtualization (CMDQV) hardware. Like the new ECMDQ feature first introduced in the ARM SMMUv3.3 specification, CMDQV adds multiple VCMDQ interfaces to supplement the single architected SMMU_CMDQ in an effort to reduce contention. This series of patches add CMDQV support with its preparational changes: * PATCH-1 to PATCH-8 are related to shared VMID feature: they are used first to improve TLB utilization, second to bind a shared VMID with a VCMDQ interface for hardware configuring requirement. * PATCH-9 and PATCH-10 are to accommodate the NVIDIA implementation with the existing arm-smmu-v3 driver. * PATCH-11 borrows the "implementation infrastructure" from the arm-smmu driver so later change can build upon it. * PATCH-12 adds an initial NVIDIA implementation related to host feature, and also adds implementation specific ->device_reset() and ->get_cmdq() callback functions. * PATCH-13 adds virtualization features using VFIO mdev interface, which allows user space hypervisor to map and get access to one of the VCMDQ interfaces of CMDQV module. ( Thinking that reviewers can get a better view of this implementation, I am attaching QEMU changes here for reference purpose: https://github.com/nicolinc/qemu/commits/dev/cmdqv_v6.0.0-rc2 The branch has all preparational changes, while I'm still integrating device model and ARM-VIRT changes, and will push them these two days, although they might not be in a good shape of being sent to review yet ) Above all, I marked RFC for this series, as I feel that we may come up some better solution. So please kindly share your reviews and insights. Thank you! Changelog v1->v2: * Added mdev interface support for hypervisor and VMs. * Added preparational changes for mdev interface implementation. * PATCH-12 Changed ->issue_cmdlist() to ->get_cmdq() for a better integration with recently merged ECMDQ-related changes. Nate Watterson (3): iommu/arm-smmu-v3: Add implementation infrastructure iommu/arm-smmu-v3: Add support for NVIDIA CMDQ-Virtualization hw iommu/nvidia-smmu-v3: Add mdev interface support Nicolin Chen (10): iommu: Add set_nesting_vmid/get_nesting_vmid functions vfio: add VFIO_IOMMU_GET_VMID and VFIO_IOMMU_SET_VMID vfio: Document VMID control for IOMMU Virtualization vfio: add set_vmid and get_vmid for vfio_iommu_type1 vfio/type1: Implement set_vmid and get_vmid vfio/type1: Set/get VMID to/from iommu driver iommu/arm-smmu-v3: Add shared VMID support for NESTING iommu/arm-smmu-v3: Add VMID alloc/free helpers iommu/arm-smmu-v3: Pass dev pointer to arm_smmu_detach_dev iommu/arm-smmu-v3: Pass cmdq pointer in arm_smmu_cmdq_issue_cmdlist() Documentation/driver-api/vfio.rst | 34 + MAINTAINERS | 2 + drivers/iommu/arm/arm-smmu-v3/Makefile | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c | 15 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 121 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 18 + .../iommu/arm/arm-smmu-v3/nvidia-smmu-v3.c | 1249 +++++++++++++++++ drivers/iommu/iommu.c | 20 + drivers/vfio/vfio.c | 25 + drivers/vfio/vfio_iommu_type1.c | 37 + include/linux/iommu.h | 5 + include/linux/vfio.h | 2 + include/uapi/linux/vfio.h | 26 + 13 files changed, 1537 insertions(+), 19 deletions(-) create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c create mode 100644 drivers/iommu/arm/arm-smmu-v3/nvidia-smmu-v3.c