| Message ID | 20211012132510.42134-1-alexandru.elisei@arm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | vfio/pci: Fix MSIX table and PBA size allocation | expand |
On Tue, 12 Oct 2021 14:25:03 +0100, Alexandru Elisei wrote: > This series is meant to rework the way the MSIX table and PBA are allocated > to prevent situations where the size allocated by kvmtool is larger than > the size of the BAR that holds them. > > Patches 1-3 are fixes for stuff I found when I was investing a bug > triggered by the incorrect sizing of the table and PBA. > > [...] Applied to kvmtool (master), thanks! [1/7] arm/gicv2m: Set errno when gicv2_update_routing() fails https://git.kernel.org/will/kvmtool/c/e3b0ade2de2b [2/7] vfio/pci.c: Remove double include for assert.h https://git.kernel.org/will/kvmtool/c/3d3dca077ae2 [3/7] pci: Fix pci_dev_* print macros https://git.kernel.org/will/kvmtool/c/34bfe5f632a4 [4/7] vfio/pci: Rename PBA offset in device descriptor to fd_offset https://git.kernel.org/will/kvmtool/c/5f44d5d6e45f [5/7] vfio/pci: Rework MSIX table and PBA physical size allocation https://git.kernel.org/will/kvmtool/c/f93acc042fbd [6/7] vfio/pci: Print an error when offset is outside of the MSIX table or PBA https://git.kernel.org/will/kvmtool/c/b20d6e302940 [7/7] vfio/pci: Align MSIX Table and PBA size to guest maximum page size https://git.kernel.org/will/kvmtool/c/39181fc6429f Cheers,
This series is meant to rework the way the MSIX table and PBA are allocated to prevent situations where the size allocated by kvmtool is larger than the size of the BAR that holds them. Patches 1-3 are fixes for stuff I found when I was investing a bug triggered by the incorrect sizing of the table and PBA. Patch 4 is a preparatory patch. Patch 5 is the proper fix. More details in the commit message. Patch 6 is there to make it easier to catch such errors if the code regresses. Patch 7 is an optimization for guests with larger page sizes than the host. Testing ======= For v2: On an AMD Seattle, host page size 4k and 64k, guest page size 4k and 64k, tested device passthrough with a Realtek RTL8168 NIC. For v1: On an AMD Seattle, host page size 4k and 64k, guest page size 4k and 64k (so 4 tests in total for each device). Tried device passthrough with a Realtek RTL8168 NIC and with a Intel 82574L NIC (not at the same time). No issues encountered, MSIX table and PBA BAR has the same layout as the physical device. On an AMD Ryzen 3900x, host and guest 4k pages, I've assigned an Intel 82574L NIC to the guest. Realtek RTL8168 doesn't work without emulating a PCI Express bus because the drivers falls back to CSI for device configuration. Everything works in the guest, the shared BAR has the same layout in the guest as the physical device. Changelog ========= Since v1: * Rebased on top of dc6646192057 ("arm64: Be more permissive when parsing the kernel header"). * Added reviewed-by tags, many thanks. * Removed comment about aligning table and pba sizes to PAGE_SIZE in vfio_pci_create_msix_table, as per Andre's suggestion. * Added a newline after local variable declaration in vfio_pci_create_msix_table. * Align MSIX table and PBA to the maximum architectural page size in #7 ("vfio/pci: Fix MSIX table and PBA size allocation"), as suggested by Andre. Alexandru Elisei (7): arm/gicv2m: Set errno when gicv2_update_routing() fails vfio/pci.c: Remove double include for assert.h pci: Fix pci_dev_* print macros vfio/pci: Rename PBA offset in device descriptor to fd_offset vfio/pci: Rework MSIX table and PBA physical size allocation vfio/pci: Print an error when offset is outside of the MSIX table or PBA vfio/pci: Align MSIX Table and PBA size to guest maximum page size arm/aarch32/include/kvm/kvm-arch.h | 4 ++ arm/aarch64/include/kvm/kvm-arch.h | 4 ++ arm/gicv2m.c | 10 ++-- include/kvm/pci.h | 10 ++-- include/kvm/vfio.h | 3 +- mips/include/kvm/kvm-arch.h | 3 ++ powerpc/include/kvm/kvm-arch.h | 3 ++ vfio/pci.c | 86 +++++++++++++++++++----------- x86/include/kvm/kvm-arch.h | 3 ++ 9 files changed, 84 insertions(+), 42 deletions(-)