| Message ID | 20221012203910.204793-1-john.allen@amd.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | SVM guest shadow stack support | expand |
On Wed, Oct 12, 2022, John Allen wrote: > AMD Zen3 and newer processors support shadow stack, a feature designed to > protect against ROP (return-oriented programming) attacks in which an attacker > manipulates return addresses on the call stack in order to execute arbitrary > code. To prevent this, shadow stacks can be allocated that are only used by > control transfer and return instructions. When a CALL instruction is issued, it > writes the return address to both the program stack and the shadow stack. When > the subsequent RET instruction is issued, it pops the return address from both > stacks and compares them. If the addresses don't match, a control-protection > exception is raised. > > Shadow stack and a related feature, Indirect Branch Tracking (IBT), are > collectively referred to as Control-flow Enforcement Technology (CET). However, > current AMD processors only support shadow stack and not IBT. > > This series adds support for shadow stack in SVM guests and builds upon the > support added in the CET guest support patch series [1] and the CET kernel > patch series [2]. Additional patches are required to support shadow stack > enabled guests in qemu [3] and glibc [4]. > > [1]: CET guest support patches > https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ > > [2]: Latest CET kernel patches > https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ That dependency chain makes me sad. Outside of a very shallow comment on the last patch, I don't plan on reviewing this until the kernel side of things gets out of our way. When that finally does happen, I'll definitely prioritize reviewing and merging this and the KVM Intel series. I'd love to see this land. Sorry :-(
On Wed, 2023-01-25 at 00:55 +0000, Sean Christopherson wrote: > On Wed, Oct 12, 2022, John Allen wrote: > > AMD Zen3 and newer processors support shadow stack, a feature > > designed to > > protect against ROP (return-oriented programming) attacks in which > > an attacker > > manipulates return addresses on the call stack in order to execute > > arbitrary > > code. To prevent this, shadow stacks can be allocated that are only > > used by > > control transfer and return instructions. When a CALL instruction > > is issued, it > > writes the return address to both the program stack and the shadow > > stack. When > > the subsequent RET instruction is issued, it pops the return > > address from both > > stacks and compares them. If the addresses don't match, a control- > > protection > > exception is raised. > > > > Shadow stack and a related feature, Indirect Branch Tracking (IBT), > > are > > collectively referred to as Control-flow Enforcement Technology > > (CET). However, > > current AMD processors only support shadow stack and not IBT. > > > > This series adds support for shadow stack in SVM guests and builds > > upon the > > support added in the CET guest support patch series [1] and the CET > > kernel > > patch series [2]. Additional patches are required to support shadow > > stack > > enabled guests in qemu [3] and glibc [4]. > > > > [1]: CET guest support patches > > https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ > > > > [2]: Latest CET kernel patches > > https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ > > That dependency chain makes me sad. > > Outside of a very shallow comment on the last patch, I don't plan on > reviewing > this until the kernel side of things gets out of our way. When that > finally > does happen, I'll definitely prioritize reviewing and merging this > and the KVM > Intel series. I'd love to see this land. I think all KVM needs is a few patches from the beginning of the host series (the FPU stuff). At one point Weijiang and I had discussed with Paolo and x86 folks that those few could go up with the KVM series if desired.
On 1/24/23 6:55 PM, Sean Christopherson wrote: > On Wed, Oct 12, 2022, John Allen wrote: >> AMD Zen3 and newer processors support shadow stack, a feature designed to >> protect against ROP (return-oriented programming) attacks in which an attacker >> manipulates return addresses on the call stack in order to execute arbitrary >> code. To prevent this, shadow stacks can be allocated that are only used by >> control transfer and return instructions. When a CALL instruction is issued, it >> writes the return address to both the program stack and the shadow stack. When >> the subsequent RET instruction is issued, it pops the return address from both >> stacks and compares them. If the addresses don't match, a control-protection >> exception is raised. >> >> Shadow stack and a related feature, Indirect Branch Tracking (IBT), are >> collectively referred to as Control-flow Enforcement Technology (CET). However, >> current AMD processors only support shadow stack and not IBT. >> >> This series adds support for shadow stack in SVM guests and builds upon the >> support added in the CET guest support patch series [1] and the CET kernel >> patch series [2]. Additional patches are required to support shadow stack >> enabled guests in qemu [3] and glibc [4]. >> >> [1]: CET guest support patches >> https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ >> >> [2]: Latest CET kernel patches >> https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ > > That dependency chain makes me sad. > > Outside of a very shallow comment on the last patch, I don't plan on reviewing > this until the kernel side of things gets out of our way. When that finally > does happen, I'll definitely prioritize reviewing and merging this and the KVM > Intel series. I'd love to see this land. > > Sorry :-( Thanks Sean, understood. This submission is mainly for community awareness, but any feedback we can get now prior to the main kernel series getting merged is much appreciated. This would give us a longer lead on addressing any concerns that the community might have and potentially allow us to get this in more quickly when the kernel series has been merged. Thanks, John
On Wed, Jan 25, 2023 at 01:11:44AM +0000, Edgecombe, Rick P wrote: > On Wed, 2023-01-25 at 00:55 +0000, Sean Christopherson wrote: > > On Wed, Oct 12, 2022, John Allen wrote: > > > AMD Zen3 and newer processors support shadow stack, a feature > > > designed to > > > protect against ROP (return-oriented programming) attacks in which > > > an attacker > > > manipulates return addresses on the call stack in order to execute > > > arbitrary > > > code. To prevent this, shadow stacks can be allocated that are only > > > used by > > > control transfer and return instructions. When a CALL instruction > > > is issued, it > > > writes the return address to both the program stack and the shadow > > > stack. When > > > the subsequent RET instruction is issued, it pops the return > > > address from both > > > stacks and compares them. If the addresses don't match, a control- > > > protection > > > exception is raised. > > > > > > Shadow stack and a related feature, Indirect Branch Tracking (IBT), > > > are > > > collectively referred to as Control-flow Enforcement Technology > > > (CET). However, > > > current AMD processors only support shadow stack and not IBT. > > > > > > This series adds support for shadow stack in SVM guests and builds > > > upon the > > > support added in the CET guest support patch series [1] and the CET > > > kernel > > > patch series [2]. Additional patches are required to support shadow > > > stack > > > enabled guests in qemu [3] and glibc [4]. > > > > > > [1]: CET guest support patches > > > > https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ > > > > > > [2]: Latest CET kernel patches > > > > https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ > > > > That dependency chain makes me sad. > > > > Outside of a very shallow comment on the last patch, I don't plan on > > reviewing > > this until the kernel side of things gets out of our way. When that > > finally > > does happen, I'll definitely prioritize reviewing and merging this > > and the KVM > > Intel series. I'd love to see this land. > > I think all KVM needs is a few patches from the beginning of the host > series (the FPU stuff). At one point Weijiang and I had discussed with > Paolo and x86 folks that those few could go up with the KVM series if > desired. Now that the baremetal series has been accepted, how do we want to proceed? I think I'd like to send a refreshed version based on the version that was accpeted, but I'd want to wait to base it on a new version of Weijiang's kvm/vmx series (if one is planned). Weijiang and Rick, Are you planning on sending a new version of the kvm/vmx series? Thanks, John
On 3/29/2023 1:51 AM, John Allen wrote: > On Wed, Jan 25, 2023 at 01:11:44AM +0000, Edgecombe, Rick P wrote: >> On Wed, 2023-01-25 at 00:55 +0000, Sean Christopherson wrote: >>> On Wed, Oct 12, 2022, John Allen wrote: >>>> AMD Zen3 and newer processors support shadow stack, a feature >>>> designed to >>>> protect against ROP (return-oriented programming) attacks in which >>>> an attacker >>>> manipulates return addresses on the call stack in order to execute >>>> arbitrary >>>> code. To prevent this, shadow stacks can be allocated that are only >>>> used by >>>> control transfer and return instructions. When a CALL instruction >>>> is issued, it >>>> writes the return address to both the program stack and the shadow >>>> stack. When >>>> the subsequent RET instruction is issued, it pops the return >>>> address from both >>>> stacks and compares them. If the addresses don't match, a control- >>>> protection >>>> exception is raised. >>>> >>>> Shadow stack and a related feature, Indirect Branch Tracking (IBT), >>>> are >>>> collectively referred to as Control-flow Enforcement Technology >>>> (CET). However, >>>> current AMD processors only support shadow stack and not IBT. >>>> >>>> This series adds support for shadow stack in SVM guests and builds >>>> upon the >>>> support added in the CET guest support patch series [1] and the CET >>>> kernel >>>> patch series [2]. Additional patches are required to support shadow >>>> stack >>>> enabled guests in qemu [3] and glibc [4]. >>>> >>>> [1]: CET guest support patches >>>> >> https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ >>>> [2]: Latest CET kernel patches >>>> >> https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ >>> That dependency chain makes me sad. >>> >>> Outside of a very shallow comment on the last patch, I don't plan on >>> reviewing >>> this until the kernel side of things gets out of our way. When that >>> finally >>> does happen, I'll definitely prioritize reviewing and merging this >>> and the KVM >>> Intel series. I'd love to see this land. >> I think all KVM needs is a few patches from the beginning of the host >> series (the FPU stuff). At one point Weijiang and I had discussed with >> Paolo and x86 folks that those few could go up with the KVM series if >> desired. > Now that the baremetal series has been accepted, how do we want to > proceed? I think I'd like to send a refreshed version based on the > version that was accpeted, but I'd want to wait to base it on a new > version of Weijiang's kvm/vmx series (if one is planned). > > Weijiang and Rick, > > Are you planning on sending a new version of the kvm/vmx series? Hi, Allen, Yes, I'm working on the new version of kvm/vmx series, will cc you when send it to community. > > Thanks, > John
On 3/29/2023 8:16 AM, Yang, Weijiang wrote: > > On 3/29/2023 1:51 AM, John Allen wrote: >> On Wed, Jan 25, 2023 at 01:11:44AM +0000, Edgecombe, Rick P wrote: >>> On Wed, 2023-01-25 at 00:55 +0000, Sean Christopherson wrote: >>>> On Wed, Oct 12, 2022, John Allen wrote: >>>>> AMD Zen3 and newer processors support shadow stack, a feature >>>>> designed to >>>>> protect against ROP (return-oriented programming) attacks in which >>>>> an attacker >>>>> manipulates return addresses on the call stack in order to execute >>>>> arbitrary >>>>> code. To prevent this, shadow stacks can be allocated that are only >>>>> used by >>>>> control transfer and return instructions. When a CALL instruction >>>>> is issued, it >>>>> writes the return address to both the program stack and the shadow >>>>> stack. When >>>>> the subsequent RET instruction is issued, it pops the return >>>>> address from both >>>>> stacks and compares them. If the addresses don't match, a control- >>>>> protection >>>>> exception is raised. >>>>> >>>>> Shadow stack and a related feature, Indirect Branch Tracking (IBT), >>>>> are >>>>> collectively referred to as Control-flow Enforcement Technology >>>>> (CET). However, >>>>> current AMD processors only support shadow stack and not IBT. >>>>> >>>>> This series adds support for shadow stack in SVM guests and builds >>>>> upon the >>>>> support added in the CET guest support patch series [1] and the CET >>>>> kernel >>>>> patch series [2]. Additional patches are required to support shadow >>>>> stack >>>>> enabled guests in qemu [3] and glibc [4]. >>>>> >>>>> [1]: CET guest support patches >>>>> >>> https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ >>> >>>>> [2]: Latest CET kernel patches >>>>> >>> https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ >>> >>>> That dependency chain makes me sad. >>>> >>>> Outside of a very shallow comment on the last patch, I don't plan on >>>> reviewing >>>> this until the kernel side of things gets out of our way. When that >>>> finally >>>> does happen, I'll definitely prioritize reviewing and merging this >>>> and the KVM >>>> Intel series. I'd love to see this land. >>> I think all KVM needs is a few patches from the beginning of the host >>> series (the FPU stuff). At one point Weijiang and I had discussed with >>> Paolo and x86 folks that those few could go up with the KVM series if >>> desired. >> Now that the baremetal series has been accepted, how do we want to >> proceed? I think I'd like to send a refreshed version based on the >> version that was accpeted, but I'd want to wait to base it on a new >> version of Weijiang's kvm/vmx series (if one is planned). >> >> Weijiang and Rick, >> >> Are you planning on sending a new version of the kvm/vmx series? > > Hi, Allen, > > Yes, I'm working on the new version of kvm/vmx series, will cc you when > > send it to community. Patch 1/7 did what I wanted to implement to support AMD SHSTK, my next version will continue refactoring them in vmx scope, then your series may pick up the helper and modify accordingly. Please note, in my series, I removed check for MSR_IA32_PL{0,1,2}_SSP since they're not supported right now, but your series supports for the MSRs, so you have to change the helper a bit to adapt to your patches. > > >> >> Thanks, >> John
On Thu, Mar 30, 2023 at 01:37:38PM +0800, Yang, Weijiang wrote: > > On 3/29/2023 8:16 AM, Yang, Weijiang wrote: > > > > On 3/29/2023 1:51 AM, John Allen wrote: > > > On Wed, Jan 25, 2023 at 01:11:44AM +0000, Edgecombe, Rick P wrote: > > > > On Wed, 2023-01-25 at 00:55 +0000, Sean Christopherson wrote: > > > > > On Wed, Oct 12, 2022, John Allen wrote: > > > > > > AMD Zen3 and newer processors support shadow stack, a feature > > > > > > designed to > > > > > > protect against ROP (return-oriented programming) attacks in which > > > > > > an attacker > > > > > > manipulates return addresses on the call stack in order to execute > > > > > > arbitrary > > > > > > code. To prevent this, shadow stacks can be allocated that are only > > > > > > used by > > > > > > control transfer and return instructions. When a CALL instruction > > > > > > is issued, it > > > > > > writes the return address to both the program stack and the shadow > > > > > > stack. When > > > > > > the subsequent RET instruction is issued, it pops the return > > > > > > address from both > > > > > > stacks and compares them. If the addresses don't match, a control- > > > > > > protection > > > > > > exception is raised. > > > > > > > > > > > > Shadow stack and a related feature, Indirect Branch Tracking (IBT), > > > > > > are > > > > > > collectively referred to as Control-flow Enforcement Technology > > > > > > (CET). However, > > > > > > current AMD processors only support shadow stack and not IBT. > > > > > > > > > > > > This series adds support for shadow stack in SVM guests and builds > > > > > > upon the > > > > > > support added in the CET guest support patch series [1] and the CET > > > > > > kernel > > > > > > patch series [2]. Additional patches are required to support shadow > > > > > > stack > > > > > > enabled guests in qemu [3] and glibc [4]. > > > > > > > > > > > > [1]: CET guest support patches > > > > > > > > > > https://lore.kernel.org/all/20220616084643.19564-1-weijiang.yang@intel.com/ > > > > > > > > > > [2]: Latest CET kernel patches > > > > > > > > > > https://lore.kernel.org/all/20220929222936.14584-1-rick.p.edgecombe@intel.com/ > > > > > > > > > That dependency chain makes me sad. > > > > > > > > > > Outside of a very shallow comment on the last patch, I don't plan on > > > > > reviewing > > > > > this until the kernel side of things gets out of our way. When that > > > > > finally > > > > > does happen, I'll definitely prioritize reviewing and merging this > > > > > and the KVM > > > > > Intel series. I'd love to see this land. > > > > I think all KVM needs is a few patches from the beginning of the host > > > > series (the FPU stuff). At one point Weijiang and I had discussed with > > > > Paolo and x86 folks that those few could go up with the KVM series if > > > > desired. > > > Now that the baremetal series has been accepted, how do we want to > > > proceed? I think I'd like to send a refreshed version based on the > > > version that was accpeted, but I'd want to wait to base it on a new > > > version of Weijiang's kvm/vmx series (if one is planned). > > > > > > Weijiang and Rick, > > > > > > Are you planning on sending a new version of the kvm/vmx series? > > > > Hi, Allen, > > > > Yes, I'm working on the new version of kvm/vmx series, will cc you when > > > > send it to community. > > Patch 1/7 did what I wanted to implement to support AMD SHSTK, my next > version > > will continue refactoring them in vmx scope, then your series may pick up > the helper > > and modify accordingly. > > Please note, in my series, I removed check for MSR_IA32_PL{0,1,2}_SSP since > they're > > not supported right now, but your series supports for the MSRs, so you have > to change > > the helper a bit to adapt to your patches. The reason we decided to include the PL{0,1,2}_SSP MSRs is that even though linux doesn't support supervisor shadow stack, a non-linux guest OS might support it and could make use of the MSRs. It could be something the vmx patches might want to account for as well Thanks, John
On Thu, Mar 30, 2023, John Allen wrote: > On Thu, Mar 30, 2023 at 01:37:38PM +0800, Yang, Weijiang wrote: > > > > On 3/29/2023 8:16 AM, Yang, Weijiang wrote: > > > > Now that the baremetal series has been accepted, how do we want to > > > > proceed? I think I'd like to send a refreshed version based on the > > > > version that was accpeted, but I'd want to wait to base it on a new > > > > version of Weijiang's kvm/vmx series (if one is planned). > > > > Patch 1/7 did what I wanted to implement to support AMD SHSTK, my next > > version will continue refactoring them in vmx scope, then� your series may > > pick up the helper and modify accordingly. > > > > Please note, in my series, I removed check for MSR_IA32_PL{0,1,2}_SSP since > > they're not supported right now, but your series supports for the MSRs, so > > you have to change the helper a bit to adapt to your patches. > > The reason we decided to include the PL{0,1,2}_SSP MSRs is that even > though linux doesn't support supervisor shadow stack, a non-linux guest > OS might support it and could make use of the MSRs. It could be > something the vmx patches might want to account for as well And emulating/virtualizing those MSRs is mandatory unless KVM can hide those MSRs without violating the architecture (been a while since I looked at CET). If the architecture does allow enumerating support for userspace but not supervisor, then ideally the two would be enabled separately in KVM, e.g. so that that if one is completely busted, we might be able to precisely revert only the broken code.
On 3/31/2023 4:05 AM, Sean Christopherson wrote: > On Thu, Mar 30, 2023, John Allen wrote: >> On Thu, Mar 30, 2023 at 01:37:38PM +0800, Yang, Weijiang wrote: >>> On 3/29/2023 8:16 AM, Yang, Weijiang wrote: >>>>> Now that the baremetal series has been accepted, how do we want to >>>>> proceed? I think I'd like to send a refreshed version based on the >>>>> version that was accpeted, but I'd want to wait to base it on a new >>>>> version of Weijiang's kvm/vmx series (if one is planned). >>> Patch 1/7 did what I wanted to implement to support AMD SHSTK, my next >>> version will continue refactoring them in vmx scope, then� your series may >>> pick up the helper and modify accordingly. >>> >>> Please note, in my series, I removed check for MSR_IA32_PL{0,1,2}_SSP since >>> they're not supported right now, but your series supports for the MSRs, so >>> you have to change the helper a bit to adapt to your patches. >> The reason we decided to include the PL{0,1,2}_SSP MSRs is that even >> though linux doesn't support supervisor shadow stack, a non-linux guest >> OS might support it and could make use of the MSRs. It could be >> something the vmx patches might want to account for as well > And emulating/virtualizing those MSRs is mandatory unless KVM can hide those MSRs > without violating the architecture (been a while since I looked at CET). If the > architecture does allow enumerating support for userspace but not supervisor, then > ideally the two would be enabled separately in KVM, e.g. so that that if one is > completely busted, we might be able to precisely revert only the broken code. OK, I'll add a separate patch to expose these supervisor MSRs but they are not accessible on Intel platform right now, i.e., resulting into #GP. Meanwhile CPUID(7,1).EDX.bit 18 is always cleared to tell guest supervisor SHSTK is not supported. Allen can modify per AMD needs.