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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v3 0/7] x86/cpu, kvm: Support AMD Automatic IBRS Date: Tue, 29 Nov 2022 17:58:09 -0600 Message-ID: <20221129235816.188737-1-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT075:EE_|MN2PR12MB4192:EE_ X-MS-Office365-Filtering-Correlation-Id: de5e2818-69da-432a-b805-08dad2659ece X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ipHAQqLKekv+7mFhLhYZrEl0Vs46LDW+hrcji+7QNjNXe7Xgexhyemg0Sc0u5xIotagFVWEyL/Q55hWCavZ8sU5R/w6ZOqhrynPgBTM1PqNVedFJMou/gxVWTLaSuQzgfVioISgsia6FUzLrhM3JJ5R/6hH5WdFenpFrSdXBl04syuvRJUwo79LKFVXuaFQjAATr+ELHli3vSULqEsYkJY3gXkeTiNhvXD+WwKZDTNB80mxYnjU4yUV/0CUMUJBBNfYgLoziZhQK35audUXvbTjHE0WswqGCw5JvLUAU3IK7pwJ0PQL7VMFjVhjwa8t0kzR2KlJn5RriTjACjkJy1t1xPKeGde4uBeVPTVCZPxd1NfsBBe82B3oiABxtVmoTbNuBWpByyq4oR+ZXdijC/nEYI0+Zy3l9aBcGSbSHasglWBFb6LYSdAesne7IZfrtejfeITuYigwrVn1uKNoTdqWgRO/AxsC6rRbPCZc7V+sccjh6c3A9UHSWORENB2NnBsUlujoaEyD8p5jcE3uXA8+j3uMdjKTjqK/IqfM3aBYgjIwx+Verir32VGdqdSFy6ZSNzpBsV482e+8C79gEAXABjgAs/WW3CuN9XN9BH9xlBvfslZHI4BF5R1XMCDXvFLx9VUF6iRboXR3Ev3qtP9xubQPiWR9U47RoUymMZ6ds2b05WmXtwpIy2a+VuGkS7rzMVHNLxyCDICLk6zBhErVtormqBPdgOlwqoueSe7BX5zZAq5GbGX0vtrmL0UpqXfYEJrhX03RDHJhop2eVA3Chh9a69ggdstvUIhSR6PjIup6cgJ4QJRrzAoqzZASJ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199015)(40470700004)(46966006)(36840700001)(47076005)(426003)(5660300002)(44832011)(7416002)(40480700001)(54906003)(41300700001)(26005)(6916009)(316002)(2616005)(40460700003)(186003)(336012)(16526019)(36756003)(8676002)(70206006)(70586007)(4326008)(82310400005)(81166007)(356005)(8936002)(1076003)(82740400003)(2906002)(83380400001)(36860700001)(86362001)(966005)(7696005)(6666004)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2022 23:58:32.3442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de5e2818-69da-432a-b805-08dad2659ece X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT075.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4192 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The AMD Zen4 core supports a new feature called Automatic IBRS (Indirect Branch Restricted Speculation). Enable Automatic IBRS by default if the CPU feature is present. It typically provides greater performance over the incumbent generic retpolines mitigation. Patches 1-3 take the existing CPUID 0x80000021 EAX feature bits that are being propagated to the guest and define scattered versions for patch 4. Patch 4 moves CPUID 0x80000021 EAX feature bits propagation code to kvm_set_cpu_caps(). Patch 5 Defines the AutoIBRS feature bit. Patch 6 Adds support for AutoIBRS by turning its EFER enablement bit on at startup if the feature is available. Patch 7 Adds support for propagating AutoIBRS to the guest. Thanks to Babu Moger for helping debug guest propagation. Babu, feel free to add your Co-developed and Signed-off-bys to patches 4 and/or 7? v3: Addressed v2 comments: - Remove Co-developed-bys. They require signed-off-bys, so co-developers need to add them themselves. - update check_null_seg_clears_base() [Boris] - Made the feature bit additions separate patches because v2 patch was clearly doing too many things at once. v2: https://lkml.org/lkml/2022/11/23/1690 - Use synthetic/scattered bits instead of introducing new leaf [Boris] - Combine the rest of the leaf's bits being used [Paolo] Note: Bits not used by the host can be moved to kvm/cpuid.c if maintainers do not want them in cpufeatures.h. - Hoist bitsetting code to kvm_set_cpu_caps(), and use cpuid_entry_override() in __do_cpuid_func() [Paolo] - Reuse SPECTRE_V2_EIBRS spectre_v2_mitigation enum [Boris, PeterZ, D.Hansen] - Change from Boris' diff: Moved setting X86_FEATURE_IBRS_ENHANCED to after BUG_EIBRS_PBRSB so PBRSB mitigations wouldn't be enabled. - Allow for users to specify "autoibrs,lfence/retpoline" instead of actively preventing the extra protections. AutoIBRS doesn't require the extra protection, but we allow it anyway. v1: https://lore.kernel.org/lkml/20221104213651.141057-2-kim.phillips@amd.com/, and https://lore.kernel.org/lkml/20221104213651.141057-4-kim.phillips@amd.com/, and https://lore.kernel.org/lkml/20221104213651.141057-3-kim.phillips@amd.com/ Signed-off-by: Kim Phillips Cc: Babu Moger Cc: Borislav Petkov Cc: Borislav Petkov Cc: Boris Ostrovsky Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Joao Martins Cc: Jonathan Corbet Cc: Konrad Rzeszutek Wilk Cc: Paolo Bonzini Cc: Sean Christopherson Cc: Thomas Gleixner Cc: David Woodhouse Cc: Greg Kroah-Hartman Cc: Juergen Gross Cc: Peter Zijlstra Cc: Tony Luck Cc: Tom Lendacky Cc: Alexey Kardashevskiy Cc: kvm@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Kim Phillips (7): x86/cpu, kvm: Define a scattered No Nested Data Breakpoints feature bit x86/cpu, kvm: Define a scattered Null Selector Clears Base feature bit x86/cpu, kvm: Make X86_FEATURE_LFENCE_RDTSC a scattered feature bit x86/cpu, kvm: Move CPUID 0x80000021 EAX feature bits propagation to kvm_set_cpu_caps x86/cpu, kvm: Define a scattered AMD Automatic IBRS feature bit x86/cpu, kvm: Support AMD Automatic IBRS x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest .../admin-guide/kernel-parameters.txt | 9 +++-- arch/x86/include/asm/cpufeatures.h | 4 ++- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 23 +++++++----- arch/x86/kernel/cpu/common.c | 11 ++++-- arch/x86/kernel/cpu/scattered.c | 4 +++ arch/x86/kvm/cpuid.c | 35 +++++++++++-------- arch/x86/kvm/reverse_cpuid.h | 24 +++++++++---- arch/x86/kvm/svm/svm.c | 3 ++ arch/x86/kvm/x86.c | 3 ++ 10 files changed, 83 insertions(+), 35 deletions(-)