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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2023 18:57:08.0922 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56f23f81-f6fd-43cc-5965-08daf017cf73 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7659 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This series adds following changes. a. Allow versioned CPUs to specify new cache_info pointers. b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the cache_info.complex_indexing. c. Introduce EPYC-Milan-v2 by adding few missing feature bits. Acked-by: Michael S. Tsirkin --- v2: Refreshed the patches on top of latest master. Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE to match the kernel name. https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phillips@amd.com/ v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/ Babu Moger (3): target/i386: Add a couple of feature bits in 8000_0008_EBX target/i386: Add feature bits for CPUID_Fn80000021_EAX target/i386: Add missing feature bits in EPYC-Milan model Michael Roth (2): target/i386: allow versioned CPUs to specify new cache_info target/i386: Add new EPYC CPU versions with updated cache_info target/i386/cpu.c | 252 +++++++++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 12 +++ 2 files changed, 259 insertions(+), 5 deletions(-)