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Thu, 4 May 2023 20:53:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT098.mail.protection.outlook.com (10.13.174.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.26 via Frontend Transport; Thu, 4 May 2023 20:53:27 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 4 May 2023 15:53:22 -0500 From: Babu Moger To: , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v4 0/7] Add EPYC-Genoa model and update previous EPYC Models Date: Thu, 4 May 2023 15:53:05 -0500 Message-ID: <20230504205313.225073-1-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT098:EE_|DS0PR12MB8415:EE_ X-MS-Office365-Filtering-Correlation-Id: 65f29cb6-31e4-44fa-50c0-08db4ce19c20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 20:53:27.1742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65f29cb6-31e4-44fa-50c0-08db4ce19c20 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8415 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This series updates the AMD EPYC models and adds new EPYC-Genoa model. Here are the features. a. Allow versioned CPUs to specify new cache_info pointers. b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the cache_info.complex_indexing. c. Introduce EPYC-Milan-v2 by adding few missing feature bits. d. Add CPU model for AMD EPYC Genoa processor series This series depends on the following recent kernel commits: 8c19b6f257fa ("KVM: x86: Propagate the AMD Automatic IBRS feature to the guest") e7862eda309e ("x86/cpu: Support AMD Automatic IBRS") 5b909d4ae59a ("x86/cpu, kvm: Add the Null Selector Clears Base feature") a9dc9ec5a1fa ("x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature") 0977cfac6e76 ("KVM: nSVM: Implement support for nested VNMI") fa4c027a7956 ("KVM: x86: Add support for SVM's Virtual NMI") --- v4: Minor text changes and function name change in patch1 (Robert Hoo). v3: Refreshed the patches on top of latest master. Add CPU model for AMD EPYC Genoa processor series (zen4) v2: Refreshed the patches on top of latest master. Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE to match the kernel name. https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phillips@amd.com/ v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/ v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.moger@amd.com/ v3: https://lore.kernel.org/kvm/20230424163401.23018-1-babu.moger@amd.com/ Babu Moger (5): target/i386: Add a couple of feature bits in 8000_0008_EBX target/i386: Add feature bits for CPUID_Fn80000021_EAX target/i386: Add missing feature bits in EPYC-Milan model target/i386: Add VNMI and automatic IBRS feature bits target/i386: Add EPYC-Genoa model to support Zen 4 processor series Michael Roth (2): target/i386: allow versioned CPUs to specify new cache_info target/i386: Add new EPYC CPU versions with updated cache_info target/i386/cpu.c | 375 +++++++++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 15 ++ 2 files changed, 384 insertions(+), 6 deletions(-)