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Thu, 25 Apr 2024 16:56:06 +0000 (GMT) From: Gerd Bayer To: Alex Williamson , Jason Gunthorpe , Niklas Schnelle Cc: kvm@vger.kernel.org, linux-s390@vger.kernel.org, Ankit Agrawal , Yishai Hadas , Halil Pasic , Julian Ruess , Gerd Bayer Subject: [PATCH v3 0/3] vfio/pci: Support 8-byte PCI loads and stores Date: Thu, 25 Apr 2024 18:56:01 +0200 Message-ID: <20240425165604.899447-1-gbayer@linux.ibm.com> X-Mailer: git-send-email 2.44.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mKS8hLn5GkthhVUk2tuGNwJDUaryPs6m X-Proofpoint-ORIG-GUID: ZPsBip09l2wGaI_T_gcmzHBhH1Jgtwec X-Proofpoint-UnRewURL: 0 URL was un-rewritten Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-25_16,2024-04-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404250123 Hi all, this all started with a single patch by Ben to enable writing a user-mode driver for a PCI device that requires 64bit register read/writes on s390. A quick grep showed that there are several other drivers for PCI devices in the kernel that use readq/writeq and eventually could use this, too. So we decided to propose this for general inclusion. A couple of suggestions for refactorizations by Jason Gunthorpe and Alex Williamson later [1], I arrived at this little series that avoids some code duplication and structures the different-size accesses in vfio_pci_core_do_io_rw() in a way that the conditional compile of 8-byte accesses no longer creates an odd split of "else-if". The initial version was tested with a PCI device on s390. This version has only been tested for reads of 1..8 byte sizes and only been compile tested for a 32bit architecture (arm). Thank you, Gerd Bayer [1] https://lore.kernel.org/all/20240422153508.2355844-1-gbayer@linux.ibm.com/ Changes v2 -> v3: - Introduce macro to generate body of different-size accesses in vfio_pci_core_do_io_rw (courtesy Alex Williamson). - Convert if-else if chain to a switch-case construct to better accommodate conditional compiles. Changes v1 -> v2: - On non 64bit architecture use at most 32bit accesses in vfio_pci_core_do_io_rw and describe that in the commit message. - Drop the run-time error on 32bit architectures. - The #endif splitting the "else if" is not really fortunate, but I'm open to suggestions. Ben Segal (1): vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer (2): vfio/pci: Extract duplicated code into macro vfio/pci: Continue to refactor vfio_pci_core_do_io_rw drivers/vfio/pci/vfio_pci_rdwr.c | 154 +++++++++++++++++-------------- include/linux/vfio_pci_core.h | 3 + 2 files changed, 90 insertions(+), 67 deletions(-)