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Peter Anvin" , Maxim Levitsky Subject: [PATCH v3 0/4] Relax canonical checks on some arch msrs Date: Thu, 15 Aug 2024 15:33:45 +0300 Message-Id: <20240815123349.729017-1-mlevitsk@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Recently we came up upon a failure where likely the guest writes 0xff4547ceb1600000 to MSR_KERNEL_GS_BASE and later on, qemu sets this value via KVM_PUT_MSRS, and is rejected by the kernel, likely due to not being canonical in 4 level paging. One of the way to trigger this is to make the guest enter SMM, which causes paging to be disabled, which SMM bios re-enables but not the whole 5 level. MSR_KERNEL_GS_BASE on the other hand continues to contain old value. I did some reverse engineering and to my surprise I found out that both Intel and AMD indeed ignore CR4.LA57 when doing canonical checks on this and other msrs and/or other arch registers (like GDT base) which contain linear addresses. V2: addressed a very good feedback from Chao Gao. Thanks! V3: also fix the nested VMX, and also fix the MSR_IA32_SYSENTER_EIP / MSR_IA32_SYSENTER_ESP Best regards, Maxim Levitsky Maxim Levitsky (4): KVM: x86: relax canonical check for some x86 architectural msrs KVM: x86: add X86_FEATURE_LA57 to governed_features KVM: nVMX: relax canonical checks on some x86 registers in vmx host state KVM: SVM: fix emulation of msr reads/writes of MSR_FS_BASE and MSR_GS_BASE arch/x86/kvm/cpuid.c | 2 ++ arch/x86/kvm/governed_features.h | 1 + arch/x86/kvm/svm/svm.c | 12 ++++++++++++ arch/x86/kvm/vmx/nested.c | 30 +++++++++++++++++++++++------- arch/x86/kvm/x86.c | 29 +++++++++++++++++++++++++++-- 5 files changed, 65 insertions(+), 9 deletions(-)