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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3dfasm10546938f8f.76.2024.11.25.03.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 03:55:42 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Jones , Anup Patel , Atish Patra Subject: [kvm-unit-tests PATCH v3 0/4] riscv: add SBI SSE extension tests Date: Mon, 25 Nov 2024 12:54:44 +0100 Message-ID: <20241125115452.1255745-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This series adds an individual test for SBI SSE extension as well as needed infrastructure for SSE support. --- V3: - Add -deps variable for test specific dependencies - Fix formatting errors/typo in sbi.h - Add missing double trap event - Alphabetize sbi-sse.c includes - Fix a6 content after unmasking event - Add SSE HART_MASK/UNMASK test - Use mv instead of move - move sbi_check_sse() definition in sbi.c - Remove sbi_sse test from unitests.cfg V2: - Rebased on origin/master and integrate it into sbi.c tests Clément Léger (4): riscv: Add "-deps" handling for tests riscv: lib: Add SBI SSE extension definitions riscv: lib: Add SSE assembly entry handling riscv: sbi: Add SSE extension tests riscv/Makefile | 9 +- lib/riscv/asm/csr.h | 2 + lib/riscv/asm/sbi.h | 83 ++++ lib/riscv/asm/sse.h | 16 + lib/riscv/sse-entry.S | 100 ++++ lib/riscv/asm-offsets.c | 9 + riscv/sbi-sse.c | 1043 +++++++++++++++++++++++++++++++++++++++ riscv/sbi.c | 3 + 8 files changed, 1262 insertions(+), 3 deletions(-) create mode 100644 lib/riscv/asm/sse.h create mode 100644 lib/riscv/sse-entry.S create mode 100644 riscv/sbi-sse.c