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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8daadbsm55496245e9.21.2025.03.07.08.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 08:15:50 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Jones , Anup Patel , Atish Patra Subject: [kvm-unit-tests PATCH v8 0/6] riscv: add SBI SSE extension tests Date: Fri, 7 Mar 2025 17:15:42 +0100 Message-ID: <20250307161549.1873770-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This series adds tests for SBI SSE extension as well as needed infrastructure for SSE support. It also adds test specific asm-offsets generation to use custom OFFSET and DEFINE from the test directory. --- V8: - Short circuit current event tests if failure happens - Remove SSE from all report strings - Indent .prio field - Add cpu_relax()/smp_rmb() where needed - Add timeout for global event ENABLED state check - Added BIT(32) aliases tests for attribute/event_id. V7: - Test ids/attributes/attributes count > 32 bits - Rename all SSE function to sbi_sse_* - Use event_id instead of event/evt - Factorize read/write test - Use virt_to_phys() for attributes read/write. - Extensively use sbiret_report_error() - Change check function return values to bool. - Added assert for stack size to be below or equal to PAGE_SIZE - Use en env variable for the maximum hart ID - Check that individual read from attributes matches the multiple attributes read. - Added multiple attributes write at once - Used READ_ONCE/WRITE_ONCE - Inject all local event at once rather than looping fopr each core. - Split test_arg for local_dispatch test so that all CPUs can run at once. - Move SSE entry and generic code to lib/riscv for other tests - Fix unmask/mask state checking V6: - Add missing $(generated-file) dependencies for "-deps" objects - Split SSE entry from sbi-asm.S to sse-asm.S and all SSE core functions since it will be useful for other tests as well (dbltrp). V5: - Update event ranges based on latest spec - Rename asm-offset-test.c to sbi-asm-offset.c V4: - Fix typo sbi_ext_ss_fid -> sbi_ext_sse_fid - Add proper asm-offset generation for tests - Move SSE specific file from lib/riscv to riscv/ V3: - Add -deps variable for test specific dependencies - Fix formatting errors/typo in sbi.h - Add missing double trap event - Alphabetize sbi-sse.c includes - Fix a6 content after unmasking event - Add SSE HART_MASK/UNMASK test - Use mv instead of move - move sbi_check_sse() definition in sbi.c - Remove sbi_sse test from unitests.cfg V2: - Rebased on origin/master and integrate it into sbi.c tests Clément Léger (6): kbuild: Allow multiple asm-offsets file to be generated riscv: Set .aux.o files as .PRECIOUS riscv: Use asm-offsets to generate SBI_EXT_HSM values riscv: lib: Add SBI SSE extension definitions lib: riscv: Add SBI SSE support riscv: sbi: Add SSE extension tests scripts/asm-offsets.mak | 22 +- riscv/Makefile | 5 +- lib/riscv/asm/csr.h | 1 + lib/riscv/asm/sbi.h | 144 ++++- lib/riscv/sbi-sse-asm.S | 103 ++++ lib/riscv/asm-offsets.c | 9 + lib/riscv/sbi.c | 76 +++ riscv/sbi-tests.h | 1 + riscv/sbi-asm.S | 6 +- riscv/sbi-asm-offsets.c | 11 + riscv/sbi-sse.c | 1215 +++++++++++++++++++++++++++++++++++++++ riscv/sbi.c | 2 + riscv/.gitignore | 1 + 13 files changed, 1584 insertions(+), 12 deletions(-) create mode 100644 lib/riscv/sbi-sse-asm.S create mode 100644 riscv/sbi-asm-offsets.c create mode 100644 riscv/sbi-sse.c create mode 100644 riscv/.gitignore