From patchwork Thu Jul 27 07:20:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13329058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CDDCC00528 for ; Thu, 27 Jul 2023 07:25:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233299AbjG0HZj (ORCPT ); Thu, 27 Jul 2023 03:25:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233290AbjG0HYN (ORCPT ); Thu, 27 Jul 2023 03:24:13 -0400 Received: from mgamail.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22E336591; Thu, 27 Jul 2023 00:15:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690442122; x=1721978122; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=BAACILCTxyqMs2Tae391dkKNJN/XDjDizeOYFsgg42A=; b=Q8zGkq7PeQe9jti7KiHDsDYNAF+jBh6svKrMNGuu0AM2TlHU682TY/Qz Buc61xQWaMJzC3fez9Wvk9wI7rLcMeRogtuoRyvoj8G539E7nsSIdMlKU SMEBX6TW5XFVJdImSu6ln15HZ9wqi14NuKqPvk1J7KpL6QtuNmgoTZP/E Sz5Vel6uXnFGu2u99ikIhqGWfmSPiO3bLOjmejo7/hw75YVdhXXf26fw9 nc9aXrAJAdG5VY7pfIm0k2srzdKumSSkGRFKJmfqavsHKoEJwS9x5qJTp 36lNyizwrVAjOUGypbAt1cdFqCIoxXpTHNFN4J/HmHWeft+Q3/iv1GdoR w==; X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="367102049" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="367102049" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2023 00:14:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="720785797" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="720785797" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2023 00:14:08 -0700 From: Haibo Xu Cc: xiaobo55x@gmail.com, haibo1.xu@intel.com, ajones@ventanamicro.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Anup Patel , Atish Patra , Sean Christopherson , Vipin Sharma , Colton Lewis , Marc Zyngier , Andrew Jones , Vishal Annapurve , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH 0/4] RISCV: Add kvm Sstc timer selftest Date: Thu, 27 Jul 2023 15:20:04 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The sstc_timer selftest is used to validate Sstc timer functionality in a guest, which sets up periodic timer interrupts and check the basic interrupt status upon its receipt. This KVM selftest was ported from aarch64 arch_timer and tested with Linux v6.5-rc3 on a Qemu riscv64 virt machine. Haibo Xu (4): tools: riscv: Add header file csr.h KVM: riscv: selftests: Add exception handling support KVM: riscv: selftests: Add guest helper to get vcpu id KVM: riscv: selftests: Add sstc_timer test tools/arch/riscv/include/asm/csr.h | 127 ++++++ tools/testing/selftests/kvm/Makefile | 2 + .../selftests/kvm/include/riscv/processor.h | 76 ++++ .../selftests/kvm/include/riscv/sstc_timer.h | 70 ++++ .../selftests/kvm/lib/riscv/handlers.S | 101 +++++ .../selftests/kvm/lib/riscv/processor.c | 74 ++++ .../testing/selftests/kvm/riscv/sstc_timer.c | 382 ++++++++++++++++++ 7 files changed, 832 insertions(+) create mode 100644 tools/arch/riscv/include/asm/csr.h create mode 100644 tools/testing/selftests/kvm/include/riscv/sstc_timer.h create mode 100644 tools/testing/selftests/kvm/lib/riscv/handlers.S create mode 100644 tools/testing/selftests/kvm/riscv/sstc_timer.c