Show patches with: Submitter = Philippe Mathieu-Daudé       |    State = Action Required       |   233 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3] target/i386: Include 'hw/i386/apic.h' locally [v3] target/i386: Include 'hw/i386/apic.h' locally 3 - - --- 2021-09-29 Philippe Mathieu-Daudé New
[v2] target/i386: Include 'hw/i386/apic.h' locally [v2] target/i386: Include 'hw/i386/apic.h' locally 1 - - --- 2021-09-29 Philippe Mathieu-Daudé New
[v7,06/40] accel/kvm: Implement AccelOpsClass::has_work() Untitled series #552825 - 1 - --- 2021-09-25 Philippe Mathieu-Daudé New
[v6,07/40] accel/kvm: Implement AccelOpsClass::has_work() Untitled series #552181 - 1 - --- 2021-09-24 Philippe Mathieu-Daudé New
[v3,24/30] target/rx: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,23/30] target/riscv: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,22/30] target/ppc: Simplify has_work() handlers accel: Move has_work() from SysemuCPUOps to AccelOpsClass - - - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,21/30] target/ppc: Introduce PowerPCCPUClass::has_work() accel: Move has_work() from SysemuCPUOps to AccelOpsClass - - - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,20/30] target/ppc: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass 1 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,19/30] target/openrisc: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,18/30] target/nios2: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,17/30] target/mips: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,16/30] target/microblaze: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,15/30] target/m68k: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,14/30] target/i386: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,13/30] target/hppa: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,12/30] target/hexagon: Remove unused has_work() handler accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,11/30] target/cris: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,10/30] target/avr: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,09/30] target/arm: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,08/30] target/alpha: Restrict has_work() handler to sysemu and TCG accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,07/30] accel/tcg: Implement AccelOpsClass::has_work() as stub accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,06/30] accel/whpx: Implement AccelOpsClass::has_work() accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,05/30] accel/kvm: Implement AccelOpsClass::has_work() accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,04/30] sysemu: Introduce AccelOpsClass::has_work() accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,03/30] hw/core: Un-inline cpu_has_work() accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,02/30] hw/core: Restrict cpu_has_work() to sysemu accel: Move has_work() from SysemuCPUOps to AccelOpsClass - 1 - --- 2021-09-02 Philippe Mathieu-Daudé New
[v3,01/30] accel/tcg: Restrict cpu_handle_halt() to sysemu accel: Move has_work() from SysemuCPUOps to AccelOpsClass - - - --- 2021-09-02 Philippe Mathieu-Daudé New
target/i386: Include 'hw/i386/apic.h' locally target/i386: Include 'hw/i386/apic.h' locally 1 - - --- 2021-09-02 Philippe Mathieu-Daudé New
[v5,11/11] .travis.yml: Add a KVM-only Aarch64 job Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,10/11] target/arm: Do not build TCG objects when TCG is off Support disabling TCG on ARM (part 2) - 1 - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,09/11] target/arm: Reorder meson.build rules Support disabling TCG on ARM (part 2) - 1 - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,05/11] target/arm: Restrict ARMv6 cpus to TCG accel Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,04/11] target/arm: Restrict ARMv5 cpus to TCG accel Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,03/11] target/arm: Restrict ARMv4 cpus to TCG accel Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,02/11] default-configs: Remove unnecessary SEMIHOSTING selection Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[v5,01/11] exec: Restrict TCG specific headers Support disabling TCG on ARM (part 2) - - - --- 2021-01-30 Philippe Mathieu-Daudé New
[PULL,66/66] docs/system: Remove deprecated 'fulong2e' machine alias [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,65/66] target/mips: Convert Rel6 LL/SC opcodes to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,64/66] target/mips: Convert Rel6 LLD/SCD opcodes to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,60/66] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,59/66] target/mips: Convert Rel6 COP1X opcode to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,58/66] target/mips: Convert Rel6 Special2 opcode to decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,56/66] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,54/66] target/mips: Extract LSA/DLSA translation generators [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,53/66] target/mips: Use decode_ase_msa() generated from decodetree [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,52/66] target/mips: Introduce decode tree bindings for MSA ASE [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,48/66] target/mips: Extract MSA helper definitions [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,47/66] target/mips: Extract MSA helpers from op_helper.c [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,46/66] target/mips: Move msa_reset() to msa_helper.c [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,43/66] target/mips: Extract msa_translate_init() from mips_tcg_init() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,42/66] target/mips: Alias MSA vector registers on FPU scalar registers [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,41/66] target/mips: Remove now unused ASE_MSA definition [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,40/66] target/mips: Simplify MSA TCG logic [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,38/66] target/mips: Simplify msa_reset() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,37/66] target/mips: Introduce ase_msa_available() helper [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 1 --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,34/66] target/mips: Only build TCG code when CONFIG_TCG is set [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,33/66] target/mips: Extract FPU specific definitions to translate.h [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,32/66] target/mips: Declare generic FPU functions in 'translate.h' [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,29/66] target/mips/translate: Add declarations for generic code [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,28/66] target/mips/translate: Extract DisasContext structure [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,27/66] target/mips: Rename translate_init.c as cpu-defs.c [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,26/66] target/mips: Move mmu_init() functions to tlb_helper.c [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,25/66] target/mips: Fix code style for checkpatch.pl [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,24/66] target/mips: Rename helper.c as tlb_helper.c [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,23/66] target/mips: Move common helpers from helper.c to cpu.c [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,20/66] target/mips: Extract FPU helpers to 'fpu_helper.h' [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 1 - --- 2021-01-07 Philippe Mathieu-Daudé New
[PULL,05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA - 2 - --- 2021-01-07 Philippe Mathieu-Daudé New
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