Show patches with: Series = Fix x2apic enablement and allow up to 32768 CPUs without IR where supported       |   7 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,8/8] x86/ioapic: Generate RTE directly from parent irqchip's MSI message Fix x2apic enablement and allow up to 32768 CPUs without IR where supported - - - --- 2020-10-09 David Woodhouse New
[v2,6/8] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID Fix x2apic enablement and allow up to 32768 CPUs without IR where supported 1 - - --- 2020-10-09 David Woodhouse New
[v2,5/8] x86/apic: Support 15 bits of APIC ID in MSI where available Fix x2apic enablement and allow up to 32768 CPUs without IR where supported - - - --- 2020-10-09 David Woodhouse New
[v2,4/8] x86/ioapic: Handle Extended Destination ID field in RTE Fix x2apic enablement and allow up to 32768 CPUs without IR where supported - - - --- 2020-10-09 David Woodhouse New
[v2,3/8] x86/apic: Always provide irq_compose_msi_msg() method for vector domain Fix x2apic enablement and allow up to 32768 CPUs without IR where supported - - - --- 2020-10-09 David Woodhouse New
[v2,2/8] x86/msi: Only use high bits of MSI address for DMAR unit Fix x2apic enablement and allow up to 32768 CPUs without IR where supported - - - --- 2020-10-09 David Woodhouse New
[v2,1/8] x86/apic: Fix x2apic enablement without interrupt remapping Fix x2apic enablement and allow up to 32768 CPUs without IR where supported - - - --- 2020-10-09 David Woodhouse New