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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 03:34:29.6161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e4e6883-18b7-4fb7-52e3-08db51077686 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000145B8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8926 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This is used to forward the host IDR values to the user space, so the hypervisor and the guest VM can learn about the underlying hardware's capabilities. Also, set the ops->hw_info_type and ops->hwpt_type_bitmap accordingly. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ include/uapi/linux/iommufd.h | 14 +++++++++++ 3 files changed, 42 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 2c53849cae30..89daf50be87b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2014,6 +2014,29 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) } } +static void *arm_smmu_hw_info(struct device *dev, u32 *length) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct iommu_hw_info_smmuv3 *info; + void *base_idr; + int i; + + if (!master || !master->smmu) + return ERR_PTR(-ENODEV); + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); + + base_idr = master->smmu->base + ARM_SMMU_IDR0; + for (i = 0; i <= 5; i++) + info->idr[i] = readl_relaxed(base_idr + 0x4 * i); + + *length = sizeof(*info); + + return info; +} + static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) { struct arm_smmu_domain *smmu_domain; @@ -2846,6 +2869,7 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, + .hw_info = arm_smmu_hw_info, .domain_alloc = arm_smmu_domain_alloc, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, @@ -2857,6 +2881,8 @@ static struct iommu_ops arm_smmu_ops = { .dev_disable_feat = arm_smmu_dev_disable_feature, .page_response = arm_smmu_page_response, .def_domain_type = arm_smmu_def_domain_type, + .hw_info_type = IOMMU_HW_INFO_TYPE_ARM_SMMUV3, + .hwpt_type_bitmap = BIT_ULL(IOMMU_HWPT_TYPE_ARM_SMMUV3), .pgsize_bitmap = -1UL, /* Restricted during device attach */ .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index b574c58a3487..5fa010c6fe20 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -14,6 +14,8 @@ #include #include +#include + /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 #define IDR0_ST_LVL GENMASK(28, 27) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 6845ce6e1e76..b1fe4c59ab82 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -534,6 +534,20 @@ struct iommu_hw_info_vtd { __aligned_u64 ecap_reg; }; +/** + * struct iommu_hw_info_smmuv3 - ARM SMMUv3 device info + * + * @flags: Must be set to 0 + * @__reserved: Must be 0 + * @idr: Implemented features for the SMMU Non-secure programming interface. + * Please refer to the chapters from 6.3.1 to 6.3.6 in the SMMUv3 Spec. + */ +struct iommu_hw_info_smmuv3 { + __u32 flags; + __u32 __reserved; + __u32 idr[6]; +}; + /** * struct iommu_hw_info - ioctl(IOMMU_DEVICE_GET_HW_INFO) * @size: sizeof(struct iommu_hw_info)