From patchwork Wed Jan 7 10:49:31 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sheng Yang X-Patchwork-Id: 1137 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n07Ak8QG030323 for ; Wed, 7 Jan 2009 02:46:09 -0800 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751580AbZAGKtj (ORCPT ); Wed, 7 Jan 2009 05:49:39 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751348AbZAGKtj (ORCPT ); Wed, 7 Jan 2009 05:49:39 -0500 Received: from mga14.intel.com ([143.182.124.37]:42786 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751580AbZAGKtg (ORCPT ); Wed, 7 Jan 2009 05:49:36 -0500 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 07 Jan 2009 02:49:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.37,225,1231142400"; d="scan'208";a="97272499" Received: from syang10-desktop.sh.intel.com (HELO syang10-desktop) ([10.239.13.47]) by azsmga001.ch.intel.com with ESMTP; 07 Jan 2009 02:49:34 -0800 Received: from yasker by syang10-desktop with local (Exim 4.69) (envelope-from ) id 1LKVyd-0005xu-PY; Wed, 07 Jan 2009 18:49:31 +0800 From: Sheng Yang To: Avi Kivity Cc: Anthony Liguori , kvm@vger.kernel.org, Sheng Yang Subject: [PATCH 6/6] kvm: expose MSI capability to guest Date: Wed, 7 Jan 2009 18:49:31 +0800 Message-Id: <1231325371-22896-7-git-send-email-sheng@linux.intel.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1231325371-22896-1-git-send-email-sheng@linux.intel.com> References: <1231325371-22896-1-git-send-email-sheng@linux.intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Sheng Yang --- qemu/hw/device-assignment.c | 111 ++++++++++++++++++++++++++++++++++++++++--- qemu/hw/device-assignment.h | 7 +++ 2 files changed, 111 insertions(+), 7 deletions(-) diff --git a/qemu/hw/device-assignment.c b/qemu/hw/device-assignment.c index 169357f..4c08b00 100644 --- a/qemu/hw/device-assignment.c +++ b/qemu/hw/device-assignment.c @@ -268,7 +268,8 @@ static void assigned_dev_pci_write_config(PCIDevice *d, uint32_t address, } if ((address >= 0x10 && address <= 0x24) || address == 0x34 || - address == 0x3c || address == 0x3d) { + address == 0x3c || address == 0x3d || + pci_access_cap_config(d, address, len)) { /* used for update-mappings (BAR emulation) */ pci_default_write_config(d, address, val, len); return; @@ -302,7 +303,8 @@ static uint32_t assigned_dev_pci_read_config(PCIDevice *d, uint32_t address, AssignedDevice *pci_dev = container_of(d, AssignedDevice, dev); if ((address >= 0x10 && address <= 0x24) || address == 0x34 || - address == 0x3c || address == 0x3d) { + address == 0x3c || address == 0x3d || + pci_access_cap_config(d, address, len)) { val = pci_default_read_config(d, address, len); DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n", (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len); @@ -331,11 +333,13 @@ do_log: DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n", (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len); - /* kill the special capabilities */ - if (address == 4 && len == 4) - val &= ~0x100000; - else if (address == 6) - val &= ~0x10; + if (!pci_dev->cap.available) { + /* kill the special capabilities */ + if (address == 4 && len == 4) + val &= ~0x100000; + else if (address == 6) + val &= ~0x10; + } return val; } @@ -566,6 +570,95 @@ void assigned_dev_update_irq(PCIDevice *d) } } +#if defined(KVM_CAP_DEVICE_MSI) && defined (KVM_CAP_GSI_ROUTE) +static void assigned_dev_update_msi(PCIDevice *pci_dev, unsigned int ctrl_pos) +{ + struct kvm_assigned_irq assigned_irq_data; + struct kvm_gsi_route_guest gsi_route; + struct kvm_gsi_route_entry_guest gsi_entry[1]; + AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice, dev); + uint8_t ctrl_byte = pci_dev->cap.config[ctrl_pos]; + + memset(&assigned_irq_data, 0, sizeof assigned_irq_data); + assigned_irq_data.assigned_dev_id = + calc_assigned_dev_id(assigned_dev->h_busnr, + (uint8_t)assigned_dev->h_devfn); + + if (ctrl_byte & PCI_MSI_FLAGS_ENABLE) { + gsi_route.entries_nr = 1; + gsi_entry[0].msi.addr_lo = *(uint32_t *)(pci_dev->cap.config + + PCI_MSI_ADDRESS_LO); + gsi_entry[0].msi.data = *(uint16_t *)(pci_dev->cap.config + + PCI_MSI_DATA_32); + gsi_entry[0].type = KVM_GSI_ROUTE_MSI; + gsi_route.entries = gsi_entry; + if (kvm_request_gsi_route(kvm_context, &gsi_route) < 0) { + perror("assigned_dev_enable_msi: kvm_request_gsi_route"); + assigned_dev->cap.state &= ~ASSIGNED_DEVICE_MSI_ENABLED; + return; + } + assigned_irq_data.guest_irq = gsi_entry[0].gsi; + assigned_irq_data.flags = KVM_DEV_IRQ_ASSIGN_ENABLE_MSI; + } else + assigned_irq_data.guest_irq = assigned_dev->girq; + + if (kvm_assign_irq(kvm_context, &assigned_irq_data) < 0) + perror("assigned_dev_enable_msi"); + if (assigned_irq_data.flags & KVM_DEV_IRQ_ASSIGN_ENABLE_MSI) { + assigned_dev->cap.state |= ASSIGNED_DEVICE_MSI_ENABLED; + pci_dev->cap.config[ctrl_pos] |= PCI_MSI_FLAGS_ENABLE; + } else { + assigned_dev->cap.state &= ~ASSIGNED_DEVICE_MSI_ENABLED; + pci_dev->cap.config[ctrl_pos] &= ~PCI_MSI_FLAGS_ENABLE; + } +} +#endif + +void assigned_device_pci_cap_write_config(PCIDevice *pci_dev, uint32_t address, + uint32_t val, int len) +{ + AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice, dev); + unsigned int pos = pci_dev->cap.start, ctrl_pos; + + pci_default_cap_write_config(pci_dev, address, val, len); +#if defined(KVM_CAP_DEVICE_MSI) && defined (KVM_CAP_GSI_ROUTE) + if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) { + ctrl_pos = pos + PCI_MSI_FLAGS; + if (address <= ctrl_pos && address + len > ctrl_pos) + assigned_dev_update_msi(pci_dev, ctrl_pos - pci_dev->cap.start); + pos += PCI_CAPABILITY_CONFIG_MSI_LENGTH; + } +#endif + return; +} + +static void assigned_device_pci_cap_init(PCIDevice *pci_dev) +{ + AssignedDevice *dev = container_of(pci_dev, AssignedDevice, dev); + int next_cap_pt; + struct pci_access *pacc; + int h_bus, h_dev, h_func; + + pci_dev->cap.length = 0; + h_bus = dev->h_busnr; + h_dev = dev->h_devfn >> 3; + h_func = dev->h_devfn & 0x07; + pacc = pci_alloc(); + pci_init(pacc); + dev->pdev = pci_get_dev(pacc, 0, h_bus, h_dev, h_func); + pci_cleanup(pacc); +#if defined(KVM_CAP_DEVICE_MSI) && defined (KVM_CAP_GSI_ROUTE) + /* Expose MSI capability + * MSI capability is the 1st capability in cap.config */ + if (pci_find_cap_offset(dev->pdev, PCI_CAP_ID_MSI)) { + dev->cap.available |= ASSIGNED_DEVICE_CAP_MSI; + pci_dev->cap.config[pci_dev->cap.length] = PCI_CAP_ID_MSI; + pci_dev->cap.length += PCI_CAPABILITY_CONFIG_MSI_LENGTH; + next_cap_pt = 1; + } +#endif +} + struct PCIDevice *init_assigned_device(AssignedDevInfo *adev, PCIBus *bus) { int r; @@ -633,6 +726,10 @@ struct PCIDevice *init_assigned_device(AssignedDevInfo *adev, PCIBus *bus) return NULL; } + pci_enable_capability_support(pci_dev, 0, NULL, + assigned_device_pci_cap_write_config, + assigned_device_pci_cap_init); + return &dev->dev; } diff --git a/qemu/hw/device-assignment.h b/qemu/hw/device-assignment.h index 2d83566..292ab32 100644 --- a/qemu/hw/device-assignment.h +++ b/qemu/hw/device-assignment.h @@ -81,6 +81,13 @@ typedef struct { unsigned char h_busnr; unsigned int h_devfn; int bound; + struct pci_dev *pdev; + struct { +#define ASSIGNED_DEVICE_CAP_MSI (1 << 0) + uint32_t available; +#define ASSIGNED_DEVICE_MSI_ENABLED (1 << 0) + uint32_t state; + } cap; } AssignedDevice; typedef struct AssignedDevInfo AssignedDevInfo;