| Message ID | 1231502556706-git-send-email-andre.przywara@amd.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Andre Przywara wrote: > Intel manual 22.3.1.2 demands that the accessed bit (bit 0 in type field) > must be set when on DS,ES,FS and GS when the selector is usable. > This fixes cross vendor migration from AMD to Intel. > > I am not sure what the real purpose of this check is, so I put this > in the VMX path and not in the SVM one. If someone has an explanation > which justifies a move, I am happy to do this. > If I understand correctly, loading a segment should set the accessed bit in the descriptor table (without virtualization there is now way to have the accessed bit clear in the segment cache), so it looks like the correct fix is to adjust svm (we already have a couple of similar fixes there).
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 9b56d21..d19e39c 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -1723,6 +1723,11 @@ static void vmx_set_segment(struct kvm_vcpu *vcpu, ar = 0xf3; } else ar = vmx_segment_access_rights(var); + + /* 22.3.1.2 demands that the accessed bit must be set on [DEFG]S */ + if (var->s && (sf->ar_bytes & AR_UNUSABLE_MASK) == 0) + ar |= 0x1; + vmcs_write32(sf->ar_bytes, ar); }
Intel manual 22.3.1.2 demands that the accessed bit (bit 0 in type field) must be set when on DS,ES,FS and GS when the selector is usable. This fixes cross vendor migration from AMD to Intel. I am not sure what the real purpose of this check is, so I put this in the VMX path and not in the SVM one. If someone has an explanation which justifies a move, I am happy to do this. Signed-off-by: Andre Przywara <andre.przywara@amd.com> --- arch/x86/kvm/vmx.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)