From patchwork Thu Mar 12 13:36:49 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sheng Yang X-Patchwork-Id: 11368 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n2CDc9B3026123 for ; Thu, 12 Mar 2009 13:38:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756528AbZCLNhY (ORCPT ); Thu, 12 Mar 2009 09:37:24 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755421AbZCLNhX (ORCPT ); Thu, 12 Mar 2009 09:37:23 -0400 Received: from mga14.intel.com ([143.182.124.37]:33052 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756542AbZCLNhG (ORCPT ); Thu, 12 Mar 2009 09:37:06 -0400 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 12 Mar 2009 06:37:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.38,350,1233561600"; d="scan'208";a="119545708" Received: from syang10-desktop.sh.intel.com (HELO syang10-desktop) ([10.239.13.189]) by azsmga001.ch.intel.com with ESMTP; 12 Mar 2009 06:37:01 -0700 Received: from yasker by syang10-desktop with local (Exim 4.69) (envelope-from ) id 1Lhl5o-0007tg-8m; Thu, 12 Mar 2009 21:37:00 +0800 From: Sheng Yang To: Avi Kivity , Marcelo Tosatti , Anthony Liguori Cc: kvm@vger.kernel.org, Sheng Yang Subject: [PATCH 06/16] Support for device capability Date: Thu, 12 Mar 2009 21:36:49 +0800 Message-Id: <1236865019-30321-7-git-send-email-sheng@linux.intel.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1236865019-30321-1-git-send-email-sheng@linux.intel.com> References: <1236865019-30321-1-git-send-email-sheng@linux.intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This framework can be easily extended to support device capability, like MSI/MSI-x. Signed-off-by: Sheng Yang --- qemu/hw/pci.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- qemu/hw/pci.h | 29 +++++++++++++++++++++ 2 files changed, 104 insertions(+), 2 deletions(-) diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c index 821646c..eca0517 100644 --- a/qemu/hw/pci.c +++ b/qemu/hw/pci.c @@ -427,8 +427,8 @@ static void pci_update_mappings(PCIDevice *d) } } -uint32_t pci_default_read_config(PCIDevice *d, - uint32_t address, int len) +static uint32_t pci_read_config(PCIDevice *d, + uint32_t address, int len) { uint32_t val; @@ -453,6 +453,45 @@ uint32_t pci_default_read_config(PCIDevice *d, return val; } +static void pci_write_config(PCIDevice *pci_dev, + uint32_t address, uint32_t val, int len) +{ + int i; + for (i = 0; i < len; i++) { + pci_dev->config[address + i] = val & 0xff; + val >>= 8; + } +} + +int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len) +{ + if (pci_dev->cap.supported && address >= pci_dev->cap.start && + (address + len) < pci_dev->cap.start + pci_dev->cap.length) + return 1; + return 0; +} + +uint32_t pci_default_cap_read_config(PCIDevice *pci_dev, + uint32_t address, int len) +{ + return pci_read_config(pci_dev, address, len); +} + +void pci_default_cap_write_config(PCIDevice *pci_dev, + uint32_t address, uint32_t val, int len) +{ + pci_write_config(pci_dev, address, val, len); +} + +uint32_t pci_default_read_config(PCIDevice *d, + uint32_t address, int len) +{ + if (pci_access_cap_config(d, address, len)) + return d->cap.config_read(d, address, len); + + return pci_read_config(d, address, len); +} + void pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { @@ -485,6 +524,11 @@ void pci_default_write_config(PCIDevice *d, return; } default_config: + if (pci_access_cap_config(d, address, len)) { + d->cap.config_write(d, address, val, len); + return; + } + /* not efficient, but simple */ addr = address; for(i = 0; i < len; i++) { @@ -905,3 +949,32 @@ PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, s->bus = pci_register_secondary_bus(&s->dev, map_irq); return s->bus; } + +int pci_enable_capability_support(PCIDevice *pci_dev, + uint32_t config_start, + PCICapConfigReadFunc *config_read, + PCICapConfigWriteFunc *config_write, + PCICapConfigInitFunc *config_init) +{ + if (!pci_dev) + return -ENODEV; + + if (config_start == 0) + pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR; + else if (config_start >= 0x40 && config_start < 0xff) + pci_dev->cap.start = config_start; + else + return -EINVAL; + + if (config_read) + pci_dev->cap.config_read = config_read; + else + pci_dev->cap.config_read = pci_default_cap_read_config; + if (config_write) + pci_dev->cap.config_write = config_write; + else + pci_dev->cap.config_write = pci_default_cap_write_config; + pci_dev->cap.supported = 1; + pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start; + return config_init(pci_dev); +} diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h index 2327215..127dbed 100644 --- a/qemu/hw/pci.h +++ b/qemu/hw/pci.h @@ -139,6 +139,12 @@ typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type); typedef int PCIUnregisterFunc(PCIDevice *pci_dev); +typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev, + uint32_t address, uint32_t val, int len); +typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev, + uint32_t address, int len); +typedef int PCICapConfigInitFunc(PCIDevice *pci_dev); + #define PCI_ADDRESS_SPACE_MEM 0x00 #define PCI_ADDRESS_SPACE_IO 0x01 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 @@ -197,6 +203,10 @@ typedef struct PCIIORegion { #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) +#define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60 +#define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40 +#define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10 + struct PCIDevice { /* PCI config space */ uint8_t config[256]; @@ -219,6 +229,14 @@ struct PCIDevice { /* Current IRQ levels. Used internally by the generic PCI code. */ int irq_state[4]; + + /* Device capability configuration space */ + struct { + int supported; + unsigned int start, length; + PCICapConfigReadFunc *config_read; + PCICapConfigWriteFunc *config_write; + } cap; }; PCIDevice *pci_register_device(PCIBus *bus, const char *name, @@ -231,6 +249,12 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num, uint32_t size, int type, PCIMapIORegionFunc *map_func); +int pci_enable_capability_support(PCIDevice *pci_dev, + uint32_t config_start, + PCICapConfigReadFunc *config_read, + PCICapConfigWriteFunc *config_write, + PCICapConfigInitFunc *config_init); + int pci_map_irq(PCIDevice *pci_dev, int pin); uint32_t pci_default_read_config(PCIDevice *d, uint32_t address, int len); @@ -238,6 +262,11 @@ void pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len); void pci_device_save(PCIDevice *s, QEMUFile *f); int pci_device_load(PCIDevice *s, QEMUFile *f); +uint32_t pci_default_cap_read_config(PCIDevice *pci_dev, + uint32_t address, int len); +void pci_default_cap_write_config(PCIDevice *pci_dev, + uint32_t address, uint32_t val, int len); +int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len); typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);