From patchwork Thu May 28 09:56:31 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 26684 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4S9tnvQ031211 for ; Thu, 28 May 2009 09:55:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755762AbZE1Jyr (ORCPT ); Thu, 28 May 2009 05:54:47 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755227AbZE1Jyr (ORCPT ); Thu, 28 May 2009 05:54:47 -0400 Received: from va3ehsobe005.messaging.microsoft.com ([216.32.180.15]:32148 "EHLO VA3EHSOBE005.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754574AbZE1Jyq (ORCPT ); Thu, 28 May 2009 05:54:46 -0400 Received: from mail97-va3-R.bigfish.com (10.7.14.247) by VA3EHSOBE005.bigfish.com (10.7.40.25) with Microsoft SMTP Server id 8.1.340.0; Thu, 28 May 2009 09:54:47 +0000 Received: from mail97-va3 (localhost.localdomain [127.0.0.1]) by mail97-va3-R.bigfish.com (Postfix) with ESMTP id 321C613C80F4; Thu, 28 May 2009 09:54:47 +0000 (UTC) X-BigFish: VPS1(zzzz1202hzzz32i62h) X-Spam-TCS-SCL: 1:0 X-FB-SS: 5, Received: by mail97-va3 (MessageSwitch) id 1243504485643884_17796; Thu, 28 May 2009 09:54:45 +0000 (UCT) Received: from ausb3extmailp02.amd.com (ausb3extmailp02.amd.com [163.181.251.22]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail97-va3.bigfish.com (Postfix) with ESMTP id 852387B0046; Thu, 28 May 2009 09:54:45 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n4S9sf7G025504; Thu, 28 May 2009 04:54:44 -0500 X-WSS-ID: 0KKCM6Z-02-MMI-01 Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 2543E123400E; Thu, 28 May 2009 04:54:34 -0500 (CDT) Received: from SAUSEXMB3.amd.com ([163.181.22.202]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 28 May 2009 04:54:39 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by SAUSEXMB3.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 28 May 2009 04:54:39 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 28 May 2009 11:54:00 +0200 From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, Andre Przywara , Christoph Egger Subject: [PATCH 1/2] use explicit 64bit storage for sysenter values Date: Thu, 28 May 2009 11:56:31 +0200 Message-ID: <1243504592-5112-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 X-OriginalArrivalTime: 28 May 2009 09:54:00.0110 (UTC) FILETIME=[3989B4E0:01C9DF7A] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since AMD does not support sysenter in 64bit mode, the VMCB fields storing the MSRs are truncated to 32bit upon VMRUN/#VMEXIT. So store the values in a separate 64bit storage to avoid truncation. Signed-off-by: Christoph Egger --- arch/x86/kvm/kvm_svm.h | 4 ++++ arch/x86/kvm/svm.c | 12 ++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/kvm_svm.h b/arch/x86/kvm/kvm_svm.h index ed66e4c..4129dc1 100644 --- a/arch/x86/kvm/kvm_svm.h +++ b/arch/x86/kvm/kvm_svm.h @@ -27,6 +27,10 @@ struct vcpu_svm { unsigned long vmcb_pa; struct svm_cpu_data *svm_data; uint64_t asid_generation; + uint64_t sysenter_cs; + uint64_t sysenter_esp; + uint64_t sysenter_eip; + struct kvm_segment user_cs; /* used in sysenter/sysexit emulation */ u64 next_rip; diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index dd667dd..f0f2885 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1978,13 +1978,13 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) break; #endif case MSR_IA32_SYSENTER_CS: - *data = svm->vmcb->save.sysenter_cs; + *data = svm->sysenter_cs; break; case MSR_IA32_SYSENTER_EIP: - *data = svm->vmcb->save.sysenter_eip; + *data = svm->sysenter_eip; break; case MSR_IA32_SYSENTER_ESP: - *data = svm->vmcb->save.sysenter_esp; + *data = svm->sysenter_esp; break; /* Nobody will change the following 5 values in the VMCB so we can safely return them on rdmsr. They will always be 0 @@ -2068,13 +2068,13 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) break; #endif case MSR_IA32_SYSENTER_CS: - svm->vmcb->save.sysenter_cs = data; + svm->sysenter_cs = data; break; case MSR_IA32_SYSENTER_EIP: - svm->vmcb->save.sysenter_eip = data; + svm->sysenter_eip = data; break; case MSR_IA32_SYSENTER_ESP: - svm->vmcb->save.sysenter_esp = data; + svm->sysenter_esp = data; break; case MSR_IA32_DEBUGCTLMSR: if (!svm_has(SVM_FEATURE_LBRV)) {