From patchwork Fri Jun 12 20:01:29 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 29954 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n5CKEYDM007293 for ; Fri, 12 Jun 2009 20:14:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752222AbZFLUO3 (ORCPT ); Fri, 12 Jun 2009 16:14:29 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755154AbZFLUO3 (ORCPT ); Fri, 12 Jun 2009 16:14:29 -0400 Received: from sg2ehsobe003.messaging.microsoft.com ([207.46.51.77]:38532 "EHLO SG2EHSOBE003.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751613AbZFLUO2 (ORCPT ); Fri, 12 Jun 2009 16:14:28 -0400 X-Greylist: delayed 908 seconds by postgrey-1.27 at vger.kernel.org; Fri, 12 Jun 2009 16:14:28 EDT Received: from mail223-sin-R.bigfish.com (10.210.100.249) by SG2EHSOBE003.bigfish.com (10.210.112.23) with Microsoft SMTP Server id 8.1.340.0; Fri, 12 Jun 2009 19:59:22 +0000 Received: from mail223-sin (localhost.localdomain [127.0.0.1]) by mail223-sin-R.bigfish.com (Postfix) with ESMTP id 0BD97CC0217; Fri, 12 Jun 2009 19:59:22 +0000 (UTC) X-SpamScore: 9 X-BigFish: VPS9(z1039oz1402Izz1202hzzz32i17ch43j62h) X-Spam-TCS-SCL: 1:0 Received: by mail223-sin (MessageSwitch) id 1244836760577926_12290; Fri, 12 Jun 2009 19:59:20 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail223-sin.bigfish.com (Postfix) with ESMTP id 04F7618A8052; Fri, 12 Jun 2009 19:59:19 +0000 (UTC) Received: from ausb3twp01.amd.com ([163.181.250.37]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n5CJx9nr019180; Fri, 12 Jun 2009 14:59:12 -0500 X-WSS-ID: 0KL566F-01-4GG-01 Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp01.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 28F571943C5; Fri, 12 Jun 2009 14:59:03 -0500 (CDT) Received: from SAUSEXMB3.amd.com ([163.181.22.202]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Jun 2009 14:59:13 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by SAUSEXMB3.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Jun 2009 14:59:13 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Jun 2009 21:58:11 +0200 From: Andre Przywara To: avi@redhat.com CC: Chris Lalancette , Joerg Roedel , kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] move performance counter MSR access interception to generic x86 KVM path Date: Fri, 12 Jun 2009 22:01:29 +0200 Message-ID: <1244836889-1365-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 X-OriginalArrivalTime: 12 Jun 2009 19:58:11.0650 (UTC) FILETIME=[1D55FA20:01C9EB98] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The performance counter MSRs are different for AMD and Intel CPUs and they are chosen mainly by the CPUID vendor string. This patch catches writes to all addresses (regardless of VMX/SVM path) and handles them in the generic MSR handler routine. Writing a 0 into the event select register is something we perfectly emulate ;-), so don't print out a warning to dmesg in this case. This fixes booting a 64bit Windows guest with an AMD CPUID on an Intel host. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 16 ---------------- arch/x86/kvm/vmx.c | 12 ------------ arch/x86/kvm/x86.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 13f6f7d..cdbd4d1 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -2143,22 +2143,6 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) else svm_disable_lbrv(svm); break; - case MSR_K7_EVNTSEL0: - case MSR_K7_EVNTSEL1: - case MSR_K7_EVNTSEL2: - case MSR_K7_EVNTSEL3: - case MSR_K7_PERFCTR0: - case MSR_K7_PERFCTR1: - case MSR_K7_PERFCTR2: - case MSR_K7_PERFCTR3: - /* - * Just discard all writes to the performance counters; this - * should keep both older linux and windows 64-bit guests - * happy - */ - pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data); - - break; case MSR_VM_HSAVE_PA: svm->hsave_msr = data; break; diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index b949db0..dc502b9 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -1025,18 +1025,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) rdtscll(host_tsc); guest_write_tsc(data, host_tsc); break; - case MSR_P6_PERFCTR0: - case MSR_P6_PERFCTR1: - case MSR_P6_EVNTSEL0: - case MSR_P6_EVNTSEL1: - /* - * Just discard all writes to the performance counters; this - * should keep both older linux and windows 64-bit guests - * happy - */ - pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data); - - break; case MSR_IA32_CR_PAT: if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { vmcs_write64(GUEST_IA32_PAT, data); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 1b91ea7..8dae08d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -849,6 +849,36 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) case MSR_IA32_MCG_STATUS: case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: return set_msr_mce(vcpu, msr, data); + + /* Performance counters are not protected by a CPUID bit, + * so we should check all of them in the generic path for the sake of + * cross vendor migration. + * Writing a zero into the event select MSRs disables them, + * which we perfectly emulate ;-). Any other value should be at least + * reported, some guests depend on them. + */ + case MSR_P6_EVNTSEL0: + case MSR_P6_EVNTSEL1: + case MSR_K7_EVNTSEL0: + case MSR_K7_EVNTSEL1: + case MSR_K7_EVNTSEL2: + case MSR_K7_EVNTSEL3: + if (data != 0) + pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " + "0x%x data 0x%llx\n", msr, data); + break; + /* at least RHEL 4 unconditionally writes to the perfctr registers, + * so we ignore writes to make it happy. + */ + case MSR_P6_PERFCTR0: + case MSR_P6_PERFCTR1: + case MSR_K7_PERFCTR0: + case MSR_K7_PERFCTR1: + case MSR_K7_PERFCTR2: + case MSR_K7_PERFCTR3: + pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " + "0x%x data 0x%llx\n", msr, data); + break; default: pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data); return 1;