From patchwork Wed Jun 17 13:50:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 30879 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n5HDlbao005228 for ; Wed, 17 Jun 2009 13:47:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763540AbZFQNrc (ORCPT ); Wed, 17 Jun 2009 09:47:32 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1763407AbZFQNrc (ORCPT ); Wed, 17 Jun 2009 09:47:32 -0400 Received: from va3ehsobe005.messaging.microsoft.com ([216.32.180.15]:43000 "EHLO VA3EHSOBE006.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1760933AbZFQNra (ORCPT ); Wed, 17 Jun 2009 09:47:30 -0400 Received: from mail115-va3-R.bigfish.com (10.7.14.252) by VA3EHSOBE006.bigfish.com (10.7.40.26) with Microsoft SMTP Server id 8.1.340.0; Wed, 17 Jun 2009 13:47:32 +0000 Received: from mail115-va3 (localhost.localdomain [127.0.0.1]) by mail115-va3-R.bigfish.com (Postfix) with ESMTP id 6098B1C1025A; Wed, 17 Jun 2009 13:47:32 +0000 (UTC) X-SpamScore: 6 X-BigFish: VPS6(zz853kzz1202hzzz32i17ch43j65h) X-Spam-TCS-SCL: 4:0 X-FB-SS: 5, Received: by mail115-va3 (MessageSwitch) id 1245246450724476_15203; Wed, 17 Jun 2009 13:47:30 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail115-va3.bigfish.com (Postfix) with ESMTP id 8CDBD16A806C; Wed, 17 Jun 2009 13:47:30 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n5HDlOqK025860; Wed, 17 Jun 2009 08:47:27 -0500 X-WSS-ID: 0KLDYAU-02-MGH-01 Received: from sausexbh2.amd.com (SAUSEXBH2.amd.com [163.181.22.102]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 2192116A03CB; Wed, 17 Jun 2009 08:47:18 -0500 (CDT) Received: from SAUSEXMB3.amd.com ([163.181.22.202]) by sausexbh2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 17 Jun 2009 08:47:25 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by SAUSEXMB3.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 17 Jun 2009 08:47:25 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 17 Jun 2009 15:47:08 +0200 From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, Andre Przywara , Christoph Egger , Amit Shah Subject: [PATCH 5/6] add sysenter emulation Date: Wed, 17 Jun 2009 15:50:35 +0200 Message-ID: <1245246636-30760-6-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1245246636-30760-1-git-send-email-andre.przywara@amd.com> References: <1245246636-30760-1-git-send-email-andre.przywara@amd.com> X-OriginalArrivalTime: 17 Jun 2009 13:47:08.0600 (UTC) FILETIME=[1B96E380:01C9EF52] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm/x86_emulate.c | 72 +++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 71 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 89bd53e..2f62aaa 100644 --- a/arch/x86/kvm/x86_emulate.c +++ b/arch/x86/kvm/x86_emulate.c @@ -1481,6 +1481,73 @@ emulate_syscall(struct x86_emulate_ctxt *ctxt) return 0; } +static int +emulate_sysenter(struct x86_emulate_ctxt *ctxt) +{ + struct decode_cache *c = &ctxt->decode; + struct kvm_segment cs, ss; + u64 msr_data; + + /* inject #UD if LOCK prefix is used */ + if (c->lock_prefix) + return -1; + + /* inject #GP if in real mode or paging is disabled */ + if (ctxt->mode == X86EMUL_MODE_REAL || + !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) { + kvm_inject_gp(ctxt->vcpu, 0); + return -1; + } + + /* XXX sysenter/sysexit have not been tested in 64bit mode. + * Therefore, we inject an #UD. + */ + if (ctxt->mode == X86EMUL_MODE_PROT64) + return -1; + + setup_syscalls_segments(ctxt, &cs, &ss); + + kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); + switch (ctxt->mode) { + case X86EMUL_MODE_PROT32: + if ((msr_data & 0xfffc) == 0x0) { + kvm_inject_gp(ctxt->vcpu, 0); + return -1; + } + break; + case X86EMUL_MODE_PROT64: + if (msr_data == 0x0) { + kvm_inject_gp(ctxt->vcpu, 0); + return -1; + } + break; + } + + ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); + cs.selector = (u16)msr_data; + cs.selector &= ~SELECTOR_RPL_MASK; + ss.selector = cs.selector + 8; + ss.selector &= ~SELECTOR_RPL_MASK; + if (ctxt->mode == X86EMUL_MODE_PROT64 + || is_long_mode(ctxt->vcpu)) { + cs.db = 0; + cs.l = 1; + cs.limit = 0xffffffff; + ss.limit = 0xffffffff; + } + + kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); + kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); + + kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); + c->eip = msr_data; + + kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); + c->regs[VCPU_REGS_RSP] = msr_data; + + return 0; +} + int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { @@ -2149,7 +2216,10 @@ twobyte_insn: c->dst.type = OP_NONE; break; case 0x34: /* sysenter */ - goto cannot_emulate; + if (emulate_sysenter(ctxt) == -1) + goto cannot_emulate; + else + goto writeback; break; case 0x35: /* sysexit */ goto cannot_emulate;