From patchwork Thu Jul 2 13:04:14 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 33659 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n62D4UJU020206 for ; Thu, 2 Jul 2009 13:04:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752246AbZGBNEX (ORCPT ); Thu, 2 Jul 2009 09:04:23 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751890AbZGBNEX (ORCPT ); Thu, 2 Jul 2009 09:04:23 -0400 Received: from wa4ehsobe005.messaging.microsoft.com ([216.32.181.15]:55490 "EHLO WA4EHSOBE006.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751802AbZGBNEW (ORCPT ); Thu, 2 Jul 2009 09:04:22 -0400 Received: from mail188-wa4-R.bigfish.com (10.8.14.247) by WA4EHSOBE006.bigfish.com (10.8.40.26) with Microsoft SMTP Server id 8.1.340.0; Thu, 2 Jul 2009 13:04:23 +0000 Received: from mail188-wa4 (localhost.localdomain [127.0.0.1]) by mail188-wa4-R.bigfish.com (Postfix) with ESMTP id 5535915D025C; Thu, 2 Jul 2009 13:04:23 +0000 (UTC) X-SpamScore: 1 X-BigFish: VPS1(zzzz1202hzzz32i65h) X-Spam-TCS-SCL: 4:0 X-FB-SS: 5, Received: by mail188-wa4 (MessageSwitch) id 1246539861885597_10166; Thu, 2 Jul 2009 13:04:21 +0000 (UCT) Received: from ausb3extmailp02.amd.com (ausb3extmailp02.amd.com [163.181.251.22]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail188-wa4.bigfish.com (Postfix) with ESMTP id B339F7A0046; Thu, 2 Jul 2009 13:04:21 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n62D4H7X017862; Thu, 2 Jul 2009 08:04:20 -0500 X-WSS-ID: 0KM5OAY-02-WQY-01 Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 2028116A03E5; Thu, 2 Jul 2009 08:04:09 -0500 (CDT) Received: from sausexmb4.amd.com ([163.181.3.15]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 2 Jul 2009 08:04:16 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb4.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 2 Jul 2009 08:04:15 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 2 Jul 2009 15:04:08 +0200 From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] fix MMIO_CONF_BASE MSR access Date: Thu, 2 Jul 2009 15:04:14 +0200 Message-ID: <1246539854-14485-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1246399795-2606-1-git-send-email-andre.przywara@amd.com> References: <1246399795-2606-1-git-send-email-andre.przywara@amd.com> X-OriginalArrivalTime: 02 Jul 2009 13:04:08.0873 (UTC) FILETIME=[96260990:01C9FB15] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some Windows versions check whether the BIOS has setup MMI/O for config space accesses on AMD Fam10h CPUs, we say "no" by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring "0" writes. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) This obsoletes the patch: "fix AMD Fam10h unhandled MSRs" from yesterday, since part of it has already been applied with an older patch. This contains only the remaining part. Thanks and Regards, Andre. diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6263991..60b2527 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -846,6 +846,13 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) return 1; } break; + case MSR_FAM10H_MMIO_CONF_BASE: + if (data != 0) { + pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " + "0x%llx\n", data); + return 1; + } + break; case MSR_AMD64_NB_CFG: break; case MSR_IA32_DEBUGCTLMSR: @@ -1054,6 +1061,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) case MSR_K7_EVNTSEL0: case MSR_K8_INT_PENDING_MSG: case MSR_AMD64_NB_CFG: + case MSR_FAM10H_MMIO_CONF_BASE: data = 0; break; case MSR_MTRRcap: