From patchwork Fri Aug 21 11:58:44 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 43099 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n7LC2veD003204 for ; Fri, 21 Aug 2009 12:02:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752869AbZHUMCx (ORCPT ); Fri, 21 Aug 2009 08:02:53 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752799AbZHUMCx (ORCPT ); Fri, 21 Aug 2009 08:02:53 -0400 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:43820 "EHLO TX2EHSOBE010.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752681AbZHUMCw (ORCPT ); Fri, 21 Aug 2009 08:02:52 -0400 Received: from mail75-tx2-R.bigfish.com (10.9.14.251) by TX2EHSOBE010.bigfish.com (10.9.40.30) with Microsoft SMTP Server id 8.1.340.0; Fri, 21 Aug 2009 12:02:53 +0000 Received: from mail75-tx2 (localhost.localdomain [127.0.0.1]) by mail75-tx2-R.bigfish.com (Postfix) with ESMTP id 6774E1AD827D; Fri, 21 Aug 2009 12:02:53 +0000 (UTC) X-SpamScore: 0 X-BigFish: VPS0(zz103dKzz1202hzzz32i203h43j62h) X-Spam-TCS-SCL: 1:0 X-FB-SS: 5, Received: by mail75-tx2 (MessageSwitch) id 1250856171845299_14873; Fri, 21 Aug 2009 12:02:51 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail75-tx2.bigfish.com (Postfix) with ESMTP id 93F6810E0058; Fri, 21 Aug 2009 12:02:51 +0000 (UTC) Received: from ausb3twp01.amd.com ([163.181.250.37]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n7LC2igu018289; Fri, 21 Aug 2009 07:02:47 -0500 X-WSS-ID: 0KOQ6SI-01-8EV-02 X-M-MSG: Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp01.amd.com (Tumbleweed MailGate 3.7.0) with ESMTP id 23C121028572; Fri, 21 Aug 2009 07:02:41 -0500 (CDT) Received: from sausexmb4.amd.com ([163.181.3.15]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 21 Aug 2009 07:02:44 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb4.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 21 Aug 2009 07:02:44 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 21 Aug 2009 14:02:40 +0200 From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, nuitari-kvm@nuitari.net, thomas.besser@kit.edu, Andre Przywara Subject: [PATCH] Fix sysenter migration issue on AMD CPUs Date: Fri, 21 Aug 2009 13:58:44 +0200 Message-ID: <1250855924-13762-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 X-OriginalArrivalTime: 21 Aug 2009 12:02:40.0584 (UTC) FILETIME=[48694C80:01CA2257] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To enable cross-vendor migration we use VMCB external variables to hold the full 64bit value of the SYSENTER MSRs, which get truncated to 32bit on AMD hardware. Since we didn't intercept these MSRs, these variables were only used in the emulation case, but were _always_ used for migration purposes. This worked fine for cross-vendor migration in compat mode, but did not work in pure legacy mode. To fix this we always intercept the SYSENTER MSRs and store the values both in the VMCB and the external variables. This works for all cases. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) Hi Avi, this should fix the problem seen by Stephane and Thomas this week. Please revert 8b2f9d194288982d654c1afef491dfdf75ec1ba9 (your proposed fix, which broke cross-vendor migration) and apply this patch afterwards. It worked for me with both 32on32 and 32on64 migration both cross-vendor and between two AMD machines. Stephane, Thomas: Can you verify this? Thanks! Regards, Andre. diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index e158a2f..7853dd3 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -101,7 +101,6 @@ struct vcpu_svm { unsigned long vmcb_pa; struct svm_cpu_data *svm_data; uint64_t asid_generation; - uint64_t sysenter_cs; uint64_t sysenter_esp; uint64_t sysenter_eip; @@ -426,8 +425,6 @@ static void svm_vcpu_init_msrpm(u32 *msrpm) #endif set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); - set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); - set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); } static void svm_enable_lbrv(struct vcpu_svm *svm) @@ -2087,7 +2084,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) break; #endif case MSR_IA32_SYSENTER_CS: - *data = svm->sysenter_cs; + *data = svm->vmcb->save.sysenter_cs; break; case MSR_IA32_SYSENTER_EIP: *data = svm->sysenter_eip; @@ -2176,13 +2173,15 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) break; #endif case MSR_IA32_SYSENTER_CS: - svm->sysenter_cs = data; + svm->vmcb->save.sysenter_cs = data; break; case MSR_IA32_SYSENTER_EIP: svm->sysenter_eip = data; + svm->vmcb->save.sysenter_eip = data; break; case MSR_IA32_SYSENTER_ESP: svm->sysenter_esp = data; + svm->vmcb->save.sysenter_esp = data; break; case MSR_IA32_DEBUGCTLMSR: if (!svm_has(SVM_FEATURE_LBRV)) {