From patchwork Fri Dec 18 08:48:43 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sheng Yang X-Patchwork-Id: 68634 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id nBI8n2WP003912 for ; Fri, 18 Dec 2009 08:49:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751470AbZLRItA (ORCPT ); Fri, 18 Dec 2009 03:49:00 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751288AbZLRIs6 (ORCPT ); Fri, 18 Dec 2009 03:48:58 -0500 Received: from mga11.intel.com ([192.55.52.93]:50091 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751234AbZLRIs5 (ORCPT ); Fri, 18 Dec 2009 03:48:57 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 18 Dec 2009 00:43:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.47,416,1257148800"; d="scan'208";a="524321163" Received: from syang10-desktop.sh.intel.com (HELO syang10-desktop) ([10.239.36.76]) by fmsmga002.fm.intel.com with ESMTP; 18 Dec 2009 00:48:38 -0800 Received: from yasker by syang10-desktop with local (Exim 4.69) (envelope-from ) id 1NLYW8-0002VT-E8; Fri, 18 Dec 2009 16:48:56 +0800 From: Sheng Yang To: Avi Kivity , Marcelo Tosatti Cc: kvm@vger.kernel.org, Sheng Yang Subject: [PATCH 2/6] x86: Add IA32_TSC_AUX MSR Date: Fri, 18 Dec 2009 16:48:43 +0800 Message-Id: <1261126127-9603-3-git-send-email-sheng@linux.intel.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1261126127-9603-1-git-send-email-sheng@linux.intel.com> References: <1261126127-9603-1-git-send-email-sheng@linux.intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4ffe09b..ac98d29 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -12,6 +12,7 @@ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ +#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ /* EFER bits: */ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 7e2b6ba..e61fb87 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -240,9 +240,9 @@ do { \ #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ (u32)((val) >> 32)) -#define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2)) +#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) -#define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) +#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) #ifdef CONFIG_SMP int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);