@@ -606,6 +606,7 @@ typedef struct CPUX86State {
SegmentCache idt; /* only base and limit are used */
target_ulong cr[5]; /* NOTE: cr1 is unused */
+ target_ulong cr8;
int32_t a20_mask;
/* FPU state */
@@ -419,6 +419,33 @@ static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
| (rhs->avl * DESC_AVL_MASK);
}
+static void kvm_set_apic_base(CPUState *env, uint64_t val)
+{
+ if (!kvm_irqchip_in_kernel())
+ cpu_set_apic_base(env, val);
+}
+
+static uint64_t kvm_get_apic_base(CPUState *env)
+{
+ if (!kvm_irqchip_in_kernel())
+ return cpu_get_apic_base(env);
+ return 0;
+}
+
+static void kvm_set_apic_tpr(CPUState *env, uint8_t val)
+{
+ if (!kvm_irqchip_in_kernel())
+ cpu_set_apic_tpr(env, val);
+}
+
+static uint8_t kvm_get_apic_tpr(CPUState *env)
+{
+ if (!kvm_irqchip_in_kernel())
+ return cpu_get_apic_tpr(env);
+ return 0;
+}
+
+
static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
{
if (set)
@@ -530,8 +557,8 @@ static int kvm_put_sregs(CPUState *env)
sregs.cr3 = env->cr[3];
sregs.cr4 = env->cr[4];
- sregs.cr8 = cpu_get_apic_tpr(env);
- sregs.apic_base = cpu_get_apic_base(env);
+ sregs.cr8 = kvm_get_apic_tpr(env);
+ sregs.apic_base = kvm_get_apic_base(env);
sregs.efer = env->efer;
@@ -639,7 +666,7 @@ static int kvm_get_sregs(CPUState *env)
env->cr[3] = sregs.cr3;
env->cr[4] = sregs.cr4;
- cpu_set_apic_base(env, sregs.apic_base);
+ kvm_set_apic_base(env, sregs.apic_base);
env->efer = sregs.efer;
//cpu_set_apic_tpr(env, sregs.cr8);
@@ -942,7 +969,7 @@ int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
run->request_interrupt_window = 0;
dprintf("setting tpr\n");
- run->cr8 = cpu_get_apic_tpr(env);
+ run->cr8 = kvm_get_apic_tpr(env);
return 0;
}
@@ -954,8 +981,8 @@ int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
else
env->eflags &= ~IF_MASK;
- cpu_set_apic_tpr(env, run->cr8);
- cpu_set_apic_base(env, run->apic_base);
+ kvm_set_apic_tpr(env, run->cr8);
+ kvm_set_apic_base(env, run->apic_base);
return 0;
}