From patchwork Wed Mar 24 16:46:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 87948 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2OGmMpv012573 for ; Wed, 24 Mar 2010 16:48:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932276Ab0CXQrx (ORCPT ); Wed, 24 Mar 2010 12:47:53 -0400 Received: from va3ehsobe002.messaging.microsoft.com ([216.32.180.12]:44285 "EHLO VA3EHSOBE002.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756607Ab0CXQrv (ORCPT ); Wed, 24 Mar 2010 12:47:51 -0400 Received: from mail82-va3-R.bigfish.com (10.7.14.241) by VA3EHSOBE002.bigfish.com (10.7.40.22) with Microsoft SMTP Server id 8.1.240.5; Wed, 24 Mar 2010 16:47:50 +0000 Received: from mail82-va3 (localhost [127.0.0.1]) by mail82-va3-R.bigfish.com (Postfix) with ESMTP id 24D8CC5813A; Wed, 24 Mar 2010 16:47:50 +0000 (UTC) X-SpamScore: -4 X-BigFish: VPS-4(zz936eMab9bhzz1202hzzz32i2a8h6bh62h) X-Spam-TCS-SCL: 1:0 X-FB-SS: 5, Received: from mail82-va3 (localhost.localdomain [127.0.0.1]) by mail82-va3 (MessageSwitch) id 1269449268706228_2153; Wed, 24 Mar 2010 16:47:48 +0000 (UTC) Received: from VA3EHSMHS033.bigfish.com (unknown [10.7.14.235]) by mail82-va3.bigfish.com (Postfix) with ESMTP id A95D2628053; Wed, 24 Mar 2010 16:47:48 +0000 (UTC) Received: from ausb3extmailp02.amd.com (163.181.251.22) by VA3EHSMHS033.bigfish.com (10.7.99.43) with Microsoft SMTP Server (TLS) id 14.0.482.39; Wed, 24 Mar 2010 16:47:48 +0000 Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with SMTP id o2OGqK5q006480; Wed, 24 Mar 2010 11:52:23 -0500 X-WSS-ID: 0KZSPBE-02-W8I-02 X-M-MSG: Received: from sausexhtp02.amd.com (sausexhtp02.amd.com [163.181.3.152]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (No client certificate requested) by ausb3twp02.amd.com (Tumbleweed MailGate 3.7.2) with ESMTP id 2B2D8FD4050; Wed, 24 Mar 2010 11:47:37 -0500 (CDT) Received: from storexhtp02.amd.com (172.24.4.4) by sausexhtp02.amd.com (163.181.3.152) with Microsoft SMTP Server (TLS) id 8.2.234.1; Wed, 24 Mar 2010 11:47:40 -0500 Received: from storexbh1.amd.com (10.1.1.17) by storexhtp02.amd.com (172.24.4.4) with Microsoft SMTP Server id 8.2.234.1; Wed, 24 Mar 2010 11:47:39 -0500 Received: from sausexmb1.amd.com ([163.181.3.156]) by storexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 24 Mar 2010 12:47:39 -0400 Received: from seurexmb1.amd.com ([165.204.9.130]) by sausexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 24 Mar 2010 11:47:38 -0500 Received: from gwo.osrc.amd.com ([165.204.16.204]) by seurexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 24 Mar 2010 17:47:36 +0100 Received: from localhost.localdomain (tronje.osrc.amd.com [165.204.15.48]) by gwo.osrc.amd.com (Postfix) with ESMTP id ED0DA49C14F; Wed, 24 Mar 2010 16:47:35 +0000 (GMT) From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] KVM: allow bit 10 to be cleared in MSR_IA32_MC4_CTL Date: Wed, 24 Mar 2010 17:46:42 +0100 Message-ID: <1269449202-8008-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.4 X-OriginalArrivalTime: 24 Mar 2010 16:47:36.0306 (UTC) FILETIME=[B511B520:01CACB71] MIME-Version: 1.0 X-Reverse-DNS: ausb3extmailp02.amd.com Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 24 Mar 2010 16:48:23 +0000 (UTC) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 097ad3a..a58c634 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -910,9 +910,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) if (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MC0_CTL + 4 * bank_num) { u32 offset = msr - MSR_IA32_MC0_CTL; - /* only 0 or all 1s can be written to IA32_MCi_CTL */ + /* only 0 or all 1s can be written to IA32_MCi_CTL + * some Linux kernels though clear bit 10 in bank 4 to + * workaround a BIOS/GART TBL issue on AMD K8s, ignore + * this to avoid an uncatched #GP in the guest + */ if ((offset & 0x3) == 0 && - data != 0 && data != ~(u64)0) + data != 0 && (data | (1 << 10)) != ~(u64)0) return -1; vcpu->arch.mce_banks[offset] = data; break;