@@ -219,6 +219,9 @@ obj-y += pcnet.o
obj-y += rtl8139.o
obj-y += e1000.o
+# Inter-VM PCI shared memory
+obj-y += ivshmem.o
+
# Hardware support
obj-i386-y = ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o
obj-i386-y += pckbd.o $(sound-obj-y) dma.o
new file mode 100644
@@ -0,0 +1,622 @@
+/*
+ * Inter-VM Shared Memory PCI device.
+ *
+ * Author:
+ * Cam Macdonell <cam@cs.ualberta.ca>
+ *
+ * Based On: cirrus_vga.c and rtl8139.c
+ *
+ * This code is licensed under the GNU GPL v2.
+ */
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <sys/io.h>
+#include <sys/ioctl.h>
+#include <sys/eventfd.h>
+#include "hw.h"
+#include "console.h"
+#include "pc.h"
+#include "pci.h"
+#include "sysemu.h"
+
+#include "msix.h"
+#include "qemu-kvm.h"
+#include "libkvm.h"
+
+#include <sys/eventfd.h>
+#include <sys/mman.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+
+#define PCI_COMMAND_IOACCESS 0x0001
+#define PCI_COMMAND_MEMACCESS 0x0002
+
+#define DEBUG_IVSHMEM
+
+#define IVSHMEM_IRQFD 0
+#define IVSHMEM_MSI 1
+
+#ifdef DEBUG_IVSHMEM
+#define IVSHMEM_DPRINTF(fmt, args...) \
+ do {printf("IVSHMEM: " fmt, ##args); } while (0)
+#else
+#define IVSHMEM_DPRINTF(fmt, args...)
+#endif
+
+#define NEW_GUEST_VAL UINT_MAX
+
+typedef struct IVShmemState {
+ PCIDevice dev;
+ uint32_t intrmask;
+ uint32_t intrstatus;
+ uint32_t doorbell;
+
+ CharDriverState * chr;
+ CharDriverState * eventfd_chr;
+ int ivshmem_mmio_io_addr;
+
+ pcibus_t mmio_addr;
+ uint8_t *ivshmem_ptr;
+ unsigned long ivshmem_offset;
+ unsigned int ivshmem_size;
+ int shm_fd; /* shared memory file descriptor */
+
+ struct kvm_ioeventfd ioeventfds[16];
+ int eventfds[16]; /* for now we have a limit of 16 inter-connected guests */
+ int eventfd_posn;
+ int num_eventfds;
+ uint32_t vectors;
+ uint32_t features;
+
+ char * shmobj;
+ uint32_t size; /*size of shared memory in MB*/
+} IVShmemState;
+
+/* registers for the Inter-VM shared memory device */
+enum ivshmem_registers {
+ IntrMask = 0,
+ IntrStatus = 4,
+ IVPosition = 8,
+ Doorbell = 12,
+};
+
+static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, int feature) {
+ return (ivs->features & (1 << feature));
+}
+
+static inline int is_power_of_two(int x) {return (x & (x-1)) == 0;}
+
+static void ivshmem_map(PCIDevice *pci_dev, int region_num,
+ pcibus_t addr, pcibus_t size, int type)
+{
+ IVShmemState *s = DO_UPCAST(IVShmemState, dev, pci_dev);
+
+ IVSHMEM_DPRINTF("addr = %u size = %u\n", (uint32_t)addr, (uint32_t)size);
+ cpu_register_physical_memory(addr, s->ivshmem_size, s->ivshmem_offset);
+
+}
+
+/* accessing registers - based on rtl8139 */
+static void ivshmem_update_irq(IVShmemState *s, int val)
+{
+ int isr;
+ isr = (s->intrstatus & s->intrmask) & 0xffffffff;
+
+ /* don't print ISR resets */
+ if (isr) {
+ IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n",
+ isr ? 1 : 0, s->intrstatus, s->intrmask);
+ }
+
+ qemu_set_irq(s->dev.irq[0], (isr != 0));
+}
+
+static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
+{
+ IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val);
+
+ s->intrmask = val;
+
+ ivshmem_update_irq(s, val);
+}
+
+static uint32_t ivshmem_IntrMask_read(IVShmemState *s)
+{
+ uint32_t ret = s->intrmask;
+
+ IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret);
+
+ return ret;
+}
+
+static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val)
+{
+ IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val);
+
+ s->intrstatus = val;
+
+ ivshmem_update_irq(s, val);
+ return;
+}
+
+static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
+{
+ uint32_t ret = s->intrstatus;
+
+ /* reading ISR clears all interrupts */
+ s->intrstatus = 0;
+
+ ivshmem_update_irq(s, 0);
+
+ return ret;
+}
+
+static void ivshmem_io_writew(void *opaque, uint8_t addr, uint32_t val)
+{
+
+ IVSHMEM_DPRINTF("We shouldn't be writing words\n");
+}
+
+static void ivshmem_io_writel(void *opaque, uint8_t addr, uint32_t val)
+{
+ IVShmemState *s = opaque;
+ u_int64_t writelong = val;
+ int dest = (addr - Doorbell)/sizeof(int);
+
+ addr &= 0xfe;
+
+ switch (addr)
+ {
+ case IntrMask:
+ ivshmem_IntrMask_write(s, val);
+ break;
+
+ case IntrStatus:
+ ivshmem_IntrStatus_write(s, val);
+ break;
+
+ default:
+ /* check doorbell range */
+ if ((addr >= Doorbell) &&
+ (addr <= Doorbell + sizeof(int) * s->num_eventfds)) {
+ IVSHMEM_DPRINTF("Writing %ld to VM %d\n", writelong, dest);
+ if (write(s->eventfds[dest], &(writelong), 8) != 8)
+ IVSHMEM_DPRINTF("error writing to eventfd\n");
+ } else {
+ IVSHMEM_DPRINTF("Invalid VM Doorbell VM %d\n", dest);
+ }
+ }
+}
+
+static void ivshmem_io_writeb(void *opaque, uint8_t addr, uint32_t val)
+{
+ IVSHMEM_DPRINTF("We shouldn't be writing bytes\n");
+}
+
+static uint32_t ivshmem_io_readw(void *opaque, uint8_t addr)
+{
+
+ IVSHMEM_DPRINTF("We shouldn't be reading words\n");
+ return 0;
+}
+
+static uint32_t ivshmem_io_readl(void *opaque, uint8_t addr)
+{
+
+ IVShmemState *s = opaque;
+ uint32_t ret;
+
+ switch (addr)
+ {
+ case IntrMask:
+ ret = ivshmem_IntrMask_read(s);
+ break;
+
+ case IntrStatus:
+ ret = ivshmem_IntrStatus_read(s);
+ break;
+
+ case IVPosition:
+ /* return my id in the ivshmem list */
+ ret = s->eventfd_posn;
+ break;
+
+ default:
+ IVSHMEM_DPRINTF("why are we reading 0x%x\n", addr);
+ ret = 0;
+ }
+
+ return ret;
+
+}
+
+static uint32_t ivshmem_io_readb(void *opaque, uint8_t addr)
+{
+ IVSHMEM_DPRINTF("We shouldn't be reading bytes\n");
+
+ return 0;
+}
+
+static void ivshmem_mmio_writeb(void *opaque,
+ target_phys_addr_t addr, uint32_t val)
+{
+ ivshmem_io_writeb(opaque, addr & 0xFF, val);
+}
+
+static void ivshmem_mmio_writew(void *opaque,
+ target_phys_addr_t addr, uint32_t val)
+{
+ ivshmem_io_writew(opaque, addr & 0xFF, val);
+}
+
+static void ivshmem_mmio_writel(void *opaque,
+ target_phys_addr_t addr, uint32_t val)
+{
+ ivshmem_io_writel(opaque, addr & 0xFF, val);
+}
+
+static uint32_t ivshmem_mmio_readb(void *opaque, target_phys_addr_t addr)
+{
+ return ivshmem_io_readb(opaque, addr & 0xFF);
+}
+
+static uint32_t ivshmem_mmio_readw(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t val = ivshmem_io_readw(opaque, addr & 0xFF);
+ return val;
+}
+
+static uint32_t ivshmem_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t val = ivshmem_io_readl(opaque, addr & 0xFF);
+ return val;
+}
+
+static CPUReadMemoryFunc *ivshmem_mmio_read[3] = {
+ ivshmem_mmio_readb,
+ ivshmem_mmio_readw,
+ ivshmem_mmio_readl,
+};
+
+static CPUWriteMemoryFunc *ivshmem_mmio_write[3] = {
+ ivshmem_mmio_writeb,
+ ivshmem_mmio_writew,
+ ivshmem_mmio_writel,
+};
+
+static void ivshmem_receive(void *opaque, const uint8_t *buf, int size)
+{
+ IVShmemState *s = opaque;
+ uint32_t val;
+
+ val = *buf;
+ if (msix_enabled(&s->dev) && (val < s->vectors))
+ msix_notify(&s->dev, val);
+ else
+ ivshmem_IntrStatus_write(s, val);
+
+ IVSHMEM_DPRINTF("ivshmem_receive 0x%02x\n", *buf);
+}
+
+static int ivshmem_can_receive(void * opaque)
+{
+ return 8;
+}
+
+static void ivshmem_event(void *opaque, int event)
+{
+// IVShmemState *s = opaque;
+ IVSHMEM_DPRINTF("ivshmem_event %d\n", event);
+}
+
+
+static CharDriverState* create_eventfd_chr_device(void * opaque, int eventfd)
+{
+ // create a event character device based on the passed eventfd
+ IVShmemState *s = opaque;
+ CharDriverState * chr;
+
+ chr = qemu_chr_open_eventfd(eventfd);
+
+ if (chr == NULL) {
+ IVSHMEM_DPRINTF("creating eventfd for eventfd %d failed\n", eventfd);
+ exit(-1);
+ }
+
+ qemu_chr_add_handlers(chr, ivshmem_can_receive, ivshmem_receive,
+ ivshmem_event, s);
+
+ return chr;
+
+}
+
+static int check_shm_size(IVShmemState *s, int shmemfd) {
+ /* check that the guest isn't going to try and map more memory than the
+ * card server allocated return -1 to indicate error */
+
+ struct stat buf;
+
+ fstat(shmemfd, &buf);
+
+ if (s->ivshmem_size > buf.st_size) {
+ fprintf(stderr, "IVSHMEM ERROR: Requested memory size greater");
+ fprintf(stderr, " than shared object size (%d > %ld)\n",
+ s->ivshmem_size, buf.st_size);
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+static void create_shared_memory_BAR(IVShmemState *s, int fd) {
+
+ s->shm_fd = fd;
+
+ s->ivshmem_offset = qemu_ram_mmap(s->shm_fd, s->ivshmem_size,
+ MAP_SHARED, 0);
+
+ s->ivshmem_ptr = qemu_get_ram_ptr(s->ivshmem_offset);
+
+ /* region for shared memory */
+ pci_register_bar(&s->dev, 2, s->ivshmem_size,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_map);
+}
+
+static int ivshmem_irqfd(PCIDevice* pdev, uint16_t vector, int fd)
+{
+ struct kvm_irqfd call = { };
+ int r;
+
+ IVSHMEM_DPRINTF("inside irqfd\n");
+ if (vector >= pdev->msix_entries_nr)
+ return -EINVAL;
+ call.fd = fd;
+ call.gsi = pdev->msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}
+
+static int ivshmem_ioeventfd(IVShmemState* s, int posn, int fd)
+{
+
+ int ret, offset;
+ struct kvm_ioeventfd iofd;
+
+ offset = Doorbell + 4 * posn;
+ iofd.addr = s->mmio_addr + offset;
+ iofd.len = 4;
+ iofd.flags = 0;
+ iofd.fd = fd;
+
+ ret = kvm_vm_ioctl(kvm_state, KVM_IOEVENTFD, &iofd);
+
+ if (ret < 0) {
+ fprintf(stderr, "error assigning ioeventfd (%d) - disabling ioeventfds\n", ret);
+ perror(strerror(ret));
+ } else IVSHMEM_DPRINTF("success assigning ioeventfd (%d)\n", ret);
+
+ return ret;
+}
+/* notify that a new guest has joined */
+static void new_guest_interrupt(IVShmemState *s)
+{
+ if (msix_enabled(&s->dev)) {
+ msix_notify(&s->dev, 0);
+ } else {
+ ivshmem_IntrStatus_write(s, NEW_GUEST_VAL);
+ }
+}
+
+static void ivshmem_read(void *opaque, const uint8_t * buf, int flags)
+{
+ IVShmemState *s = opaque;
+ int incoming_fd, tmp_fd;
+ long incoming_posn;
+
+ memcpy(&incoming_posn, buf, sizeof(long));
+ /* pick off s->chr->msgfd and store it, posn should accompany msg */
+ tmp_fd = qemu_chr_get_msgfd(s->chr);
+ IVSHMEM_DPRINTF("posn is %ld, fd is %d\n", incoming_posn, tmp_fd);
+
+ if (tmp_fd == -1) {
+ s->eventfd_posn = incoming_posn;
+ return;
+ }
+
+ /* because of the implementation of get_msgfd, we need a dup */
+ incoming_fd = dup(tmp_fd);
+
+ /* if the position is -1, then it's shared memory region fd */
+ if (incoming_posn == -1) {
+
+ s->num_eventfds = 0;
+
+ if (check_shm_size(s, incoming_fd) == -1) {
+ exit(-1);
+ }
+
+ /* creating a BAR in qemu_chr callback may be crazy */
+ create_shared_memory_BAR(s, incoming_fd);
+
+ return;
+ }
+
+ if (ivshmem_has_feature(s, IVSHMEM_IRQFD)) {
+ /* allocate ioeventfd for the new guest */
+ ivshmem_ioeventfd(s, incoming_posn, s->eventfds[incoming_posn]);
+ }
+
+ /* this is an eventfd for a particular guest VM */
+ IVSHMEM_DPRINTF("eventfds[%ld] = %d\n", incoming_posn, incoming_fd);
+ s->eventfds[incoming_posn] = incoming_fd;
+
+ /* keep track of the maximum VM ID */
+ if (incoming_posn > s->num_eventfds) {
+ s->num_eventfds = incoming_posn;
+ }
+
+ if (incoming_posn == s->eventfd_posn) {
+ if (ivshmem_has_feature(s, IVSHMEM_IRQFD)) {
+ /* setup irqfd for this VM's eventfd */
+ /* vector is set to 1 */
+ ivshmem_irqfd(&s->dev, 1, s->eventfds[s->eventfd_posn]);
+ } else {
+ /* initialize char device for callback on my eventfd */
+ s->eventfd_chr = create_eventfd_chr_device(s, s->eventfds[s->eventfd_posn]);
+ }
+ } else {
+ new_guest_interrupt(s);
+ }
+
+ return;
+}
+
+static void ivshmem_reset(DeviceState *d)
+{
+ return;
+}
+
+static void ivshmem_mmio_map(PCIDevice *pci_dev, int region_num,
+ pcibus_t addr, pcibus_t size, int type)
+{
+ IVShmemState *s = DO_UPCAST(IVShmemState, dev, pci_dev);
+
+ s->mmio_addr = addr;
+ cpu_register_physical_memory(addr + 0, 0x400, s->ivshmem_mmio_io_addr);
+
+ /* now that our mmio region has been allocated, we can receive
+ * the file descriptors */
+ qemu_chr_add_handlers(s->chr, ivshmem_can_receive, ivshmem_read,
+ ivshmem_event, s);
+
+}
+
+static int pci_ivshmem_init(PCIDevice *dev)
+{
+ IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
+ uint8_t *pci_conf;
+ int i;
+
+ /* BARs must be a power of 2 */
+ if (is_power_of_two(s->size))
+ s->ivshmem_size = s->size * 1024* 1024;
+ else {
+ fprintf(stderr, "ivshmem: size must be power of 2\n");
+ exit(1);
+ }
+
+ /* IRQFD requires MSI */
+ if (ivshmem_has_feature(s, IVSHMEM_IRQFD) &&
+ !ivshmem_has_feature(s, IVSHMEM_MSI)) {
+ fprintf(stderr, "ivshmem: ioeventfd/irqfd requires MSI\n");
+ exit(1);
+ }
+
+ pci_conf = s->dev.config;
+ pci_conf[0x00] = 0xf4; // Qumranet vendor ID 0x5002
+ pci_conf[0x01] = 0x1a;
+ pci_conf[0x02] = 0x10;
+ pci_conf[0x03] = 0x11;
+ pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
+ pci_conf[0x0a] = 0x00; // RAM controller
+ pci_conf[0x0b] = 0x05;
+ pci_conf[0x0e] = 0x00; // header_type
+
+ s->ivshmem_mmio_io_addr = cpu_register_io_memory(ivshmem_mmio_read,
+ ivshmem_mmio_write, s);
+ /* region for registers*/
+ pci_register_bar(&s->dev, 0, 0x400,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_mmio_map);
+
+ if ((s->chr != NULL) && (strncmp(s->chr->filename, "unix:", 5) == 0)) {
+ /* if we get a UNIX socket as the parameter we will talk
+ * to the ivshmem server later once the MMIO BAR is actually
+ * allocated (see ivshmem_mmio_map) */
+
+ IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
+ s->chr->filename);
+
+ s->eventfd_posn = -1;
+
+ } else {
+ /* just map the file immediately, we're not using a server */
+ int fd;
+
+ IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj);
+
+ if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR,
+ S_IRWXU|S_IRWXG|S_IRWXO)) < 0) {
+ fprintf(stderr, "kvm_ivshmem: could not open shared file\n");
+ exit(-1);
+ }
+
+ /* mmap onto PCI device's memory */
+ if (ftruncate(fd, s->ivshmem_size) != 0) {
+ fprintf(stderr, "kvm_ivshmem: could not truncate shared file\n");
+ }
+
+ create_shared_memory_BAR(s, fd);
+
+ }
+
+ IVSHMEM_DPRINTF("shared memory size is = %d\n", s->size);
+
+ pci_conf[PCI_INTERRUPT_PIN] = 1; // we are going to support interrupts
+
+ /* allocate the MSI-X vectors */
+ if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
+
+ if (!msix_init(&s->dev, s->vectors, 1, 0)) {
+ pci_register_bar(&s->dev, 1,
+ msix_bar_size(&s->dev),
+ PCI_BASE_ADDRESS_SPACE_MEMORY,
+ msix_mmio_map);
+ IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
+ } else {
+ IVSHMEM_DPRINTF("msix initialization failed\n");
+ }
+
+ /* 'activate' the vectors */
+ for (i = 0; i < s->vectors; i++) {
+ msix_vector_use(&s->dev, i);
+ }
+ }
+
+ return 0;
+}
+
+static int pci_ivshmem_uninit(PCIDevice *dev)
+{
+ IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
+
+ cpu_unregister_io_memory(s->ivshmem_mmio_io_addr);
+
+ return 0;
+}
+
+static PCIDeviceInfo ivshmem_info = {
+ .qdev.name = "ivshmem",
+ .qdev.size = sizeof(IVShmemState),
+ .qdev.reset = ivshmem_reset,
+ .init = pci_ivshmem_init,
+ .exit = pci_ivshmem_uninit,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_CHR("chardev", IVShmemState, chr),
+ DEFINE_PROP_UINT32("size", IVShmemState, size, 0),
+ DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 2),
+ DEFINE_PROP_BIT("irqfd", IVShmemState, features, IVSHMEM_IRQFD, false),
+ DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
+ DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void ivshmem_register_devices(void)
+{
+ pci_qdev_register(&ivshmem_info);
+}
+
+device_init(ivshmem_register_devices)
@@ -2074,6 +2074,12 @@ static void tcp_chr_read(void *opaque)
}
}
+CharDriverState *qemu_chr_open_eventfd(int eventfd){
+
+ return qemu_chr_open_fd(eventfd, eventfd);
+
+}
+
static void tcp_chr_connect(void *opaque)
{
CharDriverState *chr = opaque;
@@ -93,6 +93,9 @@ void qemu_chr_info_print(Monitor *mon, const QObject *ret_data);
void qemu_chr_info(Monitor *mon, QObject **ret_data);
CharDriverState *qemu_chr_find(const char *name);
+/* add an eventfd to the qemu devices that are polled */
+CharDriverState *qemu_chr_open_eventfd(int eventfd);
+
extern int term_escape_char;
/* async I/O support */