From patchwork Tue Apr 27 10:38:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joerg Roedel X-Patchwork-Id: 95367 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3RAiKZn020876 for ; Tue, 27 Apr 2010 10:44:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754759Ab0D0KjH (ORCPT ); Tue, 27 Apr 2010 06:39:07 -0400 Received: from va3ehsobe001.messaging.microsoft.com ([216.32.180.11]:3909 "EHLO VA3EHSOBE001.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754698Ab0D0KjE (ORCPT ); Tue, 27 Apr 2010 06:39:04 -0400 Received: from mail145-va3-R.bigfish.com (10.7.14.236) by VA3EHSOBE001.bigfish.com (10.7.40.21) with Microsoft SMTP Server id 8.1.340.0; Tue, 27 Apr 2010 10:39:02 +0000 Received: from mail145-va3 (localhost.localdomain [127.0.0.1]) by mail145-va3-R.bigfish.com (Postfix) with ESMTP id D8400D2031D; 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Tue, 27 Apr 2010 05:38:50 -0500 (CDT) Received: from storexhtp01.amd.com (172.24.4.3) by sausexhtp01.amd.com (163.181.3.165) with Microsoft SMTP Server (TLS) id 8.2.234.1; Tue, 27 Apr 2010 03:38:53 -0700 Received: from storexbh1.amd.com (10.1.1.17) by storexhtp01.amd.com (172.24.4.3) with Microsoft SMTP Server id 8.2.234.1; Tue, 27 Apr 2010 03:38:51 -0700 Received: from sausexmb1.amd.com ([163.181.3.156]) by storexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 27 Apr 2010 06:38:51 -0400 Received: from seurexmb1.amd.com ([165.204.9.130]) by sausexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Apr 2010 05:38:48 -0500 Received: from lemmy.osrc.amd.com ([165.204.15.93]) by seurexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 27 Apr 2010 12:38:36 +0200 Received: by lemmy.osrc.amd.com (Postfix, from userid 41430) id 2AEACC9B7D; Tue, 27 Apr 2010 12:38:36 +0200 (CEST) From: Joerg Roedel To: Avi Kivity , Marcelo Tosatti CC: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel Subject: [PATCH 19/22] KVM: MMU: Introduce init_kvm_nested_mmu() Date: Tue, 27 Apr 2010 12:38:29 +0200 Message-ID: <1272364712-17425-20-git-send-email-joerg.roedel@amd.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1272364712-17425-1-git-send-email-joerg.roedel@amd.com> References: <1272364712-17425-1-git-send-email-joerg.roedel@amd.com> X-OriginalArrivalTime: 27 Apr 2010 10:38:36.0183 (UTC) FILETIME=[CA928A70:01CAE5F5] MIME-Version: 1.0 X-Reverse-DNS: ausb3extmailp02.amd.com Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 27 Apr 2010 10:44:26 +0000 (UTC) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 8bd40b5..af89e71 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2136,6 +2136,25 @@ static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 *error) return gpa; } +static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 *error) +{ + gpa_t t_gpa; + u32 access; + u32 err; + + BUG_ON(!vcpu->arch.mmu.nested); + + /* NPT walks are treated as user writes */ + access = PFERR_WRITE_MASK | PFERR_USER_MASK; + t_gpa = vcpu->arch.nested_mmu.gva_to_gpa(vcpu, gpa, access, &err); + if (t_gpa == UNMAPPED_GVA) { + vcpu->arch.fault_address = gpa; + vcpu->arch.fault_error_code = err | PFERR_NESTED_MASK; + } + + return t_gpa; +} + static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, u32 *error) { @@ -2465,11 +2484,45 @@ static int init_kvm_softmmu(struct kvm_vcpu *vcpu) return r; } +static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) +{ + struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; + struct kvm_mmu *h_context = &vcpu->arch.mmu; + + g_context->get_cr3 = get_cr3; + g_context->translate_gpa = translate_nested_gpa; + g_context->inject_page_fault = kvm_inject_page_fault; + + /* + * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The + * translation of l2_gpa to l1_gpa addresses is done using the + * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa + * functions between mmu and nested_mmu are swapped. + */ + if (!is_paging(vcpu)) { + g_context->root_level = 0; + h_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; + } else if (is_long_mode(vcpu)) { + g_context->root_level = PT64_ROOT_LEVEL; + h_context->gva_to_gpa = paging64_gva_to_gpa_nested; + } else if (is_pae(vcpu)) { + g_context->root_level = PT32E_ROOT_LEVEL; + h_context->gva_to_gpa = paging64_gva_to_gpa_nested; + } else { + g_context->root_level = PT32_ROOT_LEVEL; + h_context->gva_to_gpa = paging32_gva_to_gpa_nested; + } + + return 0; +} + static int init_kvm_mmu(struct kvm_vcpu *vcpu) { vcpu->arch.update_pte.pfn = bad_pfn; - if (tdp_enabled) + if (vcpu->arch.mmu.nested) + return init_kvm_nested_mmu(vcpu); + else if (tdp_enabled) return init_kvm_tdp_mmu(vcpu); else return init_kvm_softmmu(vcpu);