From patchwork Wed Jul 14 05:45:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduard - Gabriel Munteanu X-Patchwork-Id: 111893 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6E5kbnG027298 for ; Wed, 14 Jul 2010 05:46:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751663Ab0GNFqe (ORCPT ); Wed, 14 Jul 2010 01:46:34 -0400 Received: from mail-bw0-f46.google.com ([209.85.214.46]:46395 "EHLO mail-bw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751427Ab0GNFqd (ORCPT ); Wed, 14 Jul 2010 01:46:33 -0400 Received: by mail-bw0-f46.google.com with SMTP id 1so678994bwz.19 for ; Tue, 13 Jul 2010 22:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:cc:subject :date:message-id:x-mailer:in-reply-to:references; bh=0+eSpk2NCa5dbB5A6E2LqVdcMzNxFC/LS7S8EY39ngM=; b=D4fE6z42Cec0N6UAwGqy7fefx7JUuiWaoiv8poF7jvsNTpELyfqJBByl9+GV/tdXHq /TlrChfipjqhVaFvn1K8K8Ps5B4qYGIojVr0oIcpX/0OoaPFG4bvdXcdWrf3iMKUj6i7 J0bDHMc51mvxziVKEwFltEFSAdq0QJHizHPb4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=uckdQGwnOSQRckaFuscRpdUWQ+7JwqsXTQ2w+g6GnqayiWOBjvA8HgMqDwkOOhfGHO tYYjy+6s2zYDZ6JS3pAvhngGJjhqZ9kGzr0itAuw4i1ho3a0sEzj7QvSeGSzDI4Mjoj3 q0vQHdcdyPk6Hcd0QeDKTySIBAF42XlX1fYSI= Received: by 10.204.127.65 with SMTP id f1mr12751928bks.55.1279086391992; Tue, 13 Jul 2010 22:46:31 -0700 (PDT) Received: from localhost ([188.25.93.67]) by mx.google.com with ESMTPS id g11sm29670898bkw.22.2010.07.13.22.46.30 (version=SSLv3 cipher=RC4-MD5); Tue, 13 Jul 2010 22:46:31 -0700 (PDT) From: Eduard - Gabriel Munteanu To: joro@8bytes.org Cc: avi@redhat.com, paul@codesourcery.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, Eduard - Gabriel Munteanu Subject: [RFC PATCH 1/7] Generic IOMMU layer Date: Wed, 14 Jul 2010 08:45:01 +0300 Message-Id: <1279086307-9596-2-git-send-email-eduard.munteanu@linux360.ro> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1279086307-9596-1-git-send-email-eduard.munteanu@linux360.ro> References: <1279086307-9596-1-git-send-email-eduard.munteanu@linux360.ro> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 14 Jul 2010 05:46:37 +0000 (UTC) diff --git a/Makefile.target b/Makefile.target index 70a9c1b..3f895ae 100644 --- a/Makefile.target +++ b/Makefile.target @@ -183,6 +183,7 @@ obj-$(CONFIG_VIRTFS) += virtio-9p.o obj-y += rwhandler.o obj-$(CONFIG_KVM) += kvm.o kvm-all.o obj-$(CONFIG_NO_KVM) += kvm-stub.o +obj-$(CONFIG_IOMMU) += iommu.o # MSI-X depends on kvm for interrupt injection, # so moved it from Makefile.objs to Makefile.target for now diff --git a/hw/iommu.c b/hw/iommu.c new file mode 100644 index 0000000..511756b --- /dev/null +++ b/hw/iommu.c @@ -0,0 +1,82 @@ +/* + * Generic IOMMU layer + * + * Copyright (c) 2010 Eduard - Gabriel Munteanu + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "iommu.h" + +struct iommu *iommu_get(DeviceState *dev, DeviceState **real_dev) +{ + BusState *bus; + + while (dev) { + bus = dev->parent_bus; + if (!bus) + goto out; + + if (bus->iommu) { + *real_dev = dev; + return bus->iommu; + } + + dev = bus->parent; + } + +out: + *real_dev = NULL; + return NULL; +} + +int __iommu_rw(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + uint8_t *buf, + int len, + int is_write) +{ + int plen, err; + target_phys_addr_t paddr; + unsigned perms; + + if (!is_write) + perms = IOMMU_PERM_READ; + else + perms = IOMMU_PERM_WRITE; + + do { + err = iommu->translate(iommu, dev, addr, &paddr, &plen, perms); + if (err) + return err; + if (plen > len) + plen = len; + + cpu_physical_memory_rw(paddr, buf, plen, is_write); + + len -= plen; + addr += plen; + buf += plen; + } while (len); + + return 0; +} diff --git a/hw/iommu.h b/hw/iommu.h new file mode 100644 index 0000000..01996a6 --- /dev/null +++ b/hw/iommu.h @@ -0,0 +1,260 @@ +#ifndef QEMU_IOMMU_H +#define QEMU_IOMMU_H + +#include "pci.h" +#include "targphys.h" +#include "qdev.h" + +/* Don't use directly. */ +struct iommu { + void *opaque; + + void (*register_device)(struct iommu *iommu, + DeviceState *dev); + int (*translate)(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + target_phys_addr_t *paddr, + int *len, + unsigned perms); + int (*start_transaction)(struct iommu *iommu, + DeviceState *dev); + void (*end_transaction)(struct iommu *iommu, + DeviceState *dev); +}; + +#define IOMMU_PERM_READ (1 << 0) +#define IOMMU_PERM_WRITE (1 << 1) + +#define IOMMU_PERM_RW (IOMMU_PERM_READ | IOMMU_PERM_WRITE) + +static inline int iommu_nop_translate(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + target_phys_addr_t *paddr, + int *len, + unsigned perms) +{ + *paddr = addr; + *len = INT_MAX; + + return 0; +} + +static inline int iommu_nop_rw(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + uint8_t *buf, + int len, + int is_write) +{ + cpu_physical_memory_rw(addr, buf, len, is_write); + + return 0; +} + +static inline int iommu_register_device(struct iommu *iommu, + DeviceState *dev) +{ + if (iommu && iommu->register_device) + iommu->register_device(iommu, dev); + + return 0; +} + +#ifdef CONFIG_IOMMU + +extern struct iommu *iommu_get(DeviceState *dev, DeviceState **real_dev); + +/** + * Translates an address for the given device and performs access checking. + * + * Defined in implementation-specific IOMMU code. + * + * @iommu IOMMU + * @dev qdev device + * @addr address to be translated + * @paddr translated address + * @len number of bytes for which the translation is valid + * @rw read or write? + * + * Returns 0 iff translation and access checking succeeded. + */ +static inline int iommu_translate(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + target_phys_addr_t *paddr, + int *len, + unsigned perms) +{ + if (iommu && iommu->translate) + return iommu->translate(iommu, dev, addr, paddr, len, perms); + + return iommu_nop_translate(iommu, dev, addr, paddr, len, perms); +} + +extern int __iommu_rw(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + uint8_t *buf, + int len, + int is_write); + +/** + * Performs I/O with address translation and access checking. + * + * Defined in generic IOMMU code. + * + * @iommu IOMMU + * @dev qdev device + * @addr address where to perform I/O + * @buf buffer to read from or write to + * @len length of the operation + * @rw read or write? + * + * Returns 0 iff the I/O operation succeeded. + */ +static inline int iommu_rw(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + uint8_t *buf, + int len, + int is_write) +{ + if (iommu && iommu->translate) + return __iommu_rw(iommu, dev, addr, buf, len, is_write); + + return iommu_nop_rw(iommu, dev, addr, buf, len, is_write); +} + +static inline int iommu_start_transaction(struct iommu *iommu, + DeviceState *dev) +{ + if (iommu && iommu->start_transaction) + return iommu->start_transaction(iommu, dev); + + return 0; +} + +static inline void iommu_end_transaction(struct iommu *iommu, + DeviceState *dev) +{ + if (iommu && iommu->end_transaction) + iommu->end_transaction(iommu, dev); +} + +#define DEFINE_LD_PHYS(suffix, size) \ +static inline uint##size##_t iommu_ld##suffix(struct iommu *iommu, \ + DeviceState *dev, \ + target_phys_addr_t addr) \ +{ \ + int len, err; \ + target_phys_addr_t paddr; \ + \ + err = iommu_translate(iommu, dev, addr, &paddr, &len, IOMMU_PERM_READ); \ + if (err || (len < size / 8)) \ + return err; \ + return ld##suffix##_phys(paddr); \ +} + +#define DEFINE_ST_PHYS(suffix, size) \ +static inline void iommu_st##suffix(struct iommu *iommu, \ + DeviceState *dev, \ + target_phys_addr_t addr, \ + uint##size##_t val) \ +{ \ + int len, err; \ + target_phys_addr_t paddr; \ + \ + err = iommu_translate(iommu, dev, addr, &paddr, &len, IOMMU_PERM_WRITE);\ + if (err || (len < size / 8)) \ + return; \ + st##suffix##_phys(paddr, val); \ +} + +#else /* CONFIG_IOMMU */ + +static inline struct iommu *iommu_get(DeviceState *dev, DeviceState **real_dev) +{ + return NULL; +} + +static inline int iommu_translate(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + target_phys_addr_t *paddr, + int *len, + unsigned perms) +{ + return iommu_nop_translate(iommu, dev, addr, paddr, len, perms); +} + +static inline int iommu_rw(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + uint8_t *buf, + int len, + int is_write) +{ + return iommu_nop_rw(iommu, dev, addr, buf, len, is_write); +} + +static inline int iommu_start_transaction(struct iommu *iommu, + DeviceState *dev) +{ + return 0; +} + +static inline void iommu_end_transaction(struct iommu *iommu, + DeviceState *dev) +{ +} + +#define DEFINE_LD_PHYS(suffix, size) \ +static inline uint##size##_t iommu_ld##suffix(struct iommu *iommu, \ + DeviceState *dev, \ + target_phys_addr_t addr) \ +{ \ + return ld##suffix##_phys(addr); \ +} + +#define DEFINE_ST_PHYS(suffix, size) \ +static inline void iommu_st##suffix(struct iommu *iommu, \ + DeviceState *dev, \ + target_phys_addr_t addr, \ + uint##size##_t val) \ +{ \ + st##suffix##_phys(addr, val); \ +} + +#endif /* CONFIG_IOMMU */ + +static inline int iommu_read(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + uint8_t *buf, + int len) +{ + return iommu_rw(iommu, dev, addr, buf, len, 0); +} + +static inline int iommu_write(struct iommu *iommu, + DeviceState *dev, + target_phys_addr_t addr, + const uint8_t *buf, + int len) +{ + return iommu_rw(iommu, dev, addr, (uint8_t *) buf, len, 1); +} + +DEFINE_LD_PHYS(ub, 8) +DEFINE_LD_PHYS(uw, 16) +DEFINE_LD_PHYS(l, 32) +DEFINE_LD_PHYS(q, 64) + +DEFINE_ST_PHYS(b, 8) +DEFINE_ST_PHYS(w, 16) +DEFINE_ST_PHYS(l, 32) +DEFINE_ST_PHYS(q, 64) + +#endif diff --git a/hw/qdev.h b/hw/qdev.h index be5ad67..deb71fd 100644 --- a/hw/qdev.h +++ b/hw/qdev.h @@ -56,6 +56,8 @@ struct BusInfo { Property *props; }; +struct iommu; + struct BusState { DeviceState *parent; BusInfo *info; @@ -64,6 +66,10 @@ struct BusState { int qdev_allocated; QLIST_HEAD(, DeviceState) children; QLIST_ENTRY(BusState) sibling; + +#ifdef CONFIG_IOMMU + struct iommu *iommu; +#endif }; struct Property {