From patchwork Mon Aug 15 14:17:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avi Kivity X-Patchwork-Id: 1067722 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7FEI1GG026614 for ; Mon, 15 Aug 2011 14:18:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753899Ab1HOOSE (ORCPT ); Mon, 15 Aug 2011 10:18:04 -0400 Received: from mx1.redhat.com ([209.132.183.28]:32196 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753662Ab1HOORp (ORCPT ); Mon, 15 Aug 2011 10:17:45 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p7FEHiV4001894 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 15 Aug 2011 10:17:44 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p7FEHhn8002090; Mon, 15 Aug 2011 10:17:43 -0400 Received: from s01.tlv.redhat.com (s01.tlv.redhat.com [10.35.255.8]) by cleopatra.tlv.redhat.com (Postfix) with ESMTP id A5FCB250B58; Mon, 15 Aug 2011 17:17:40 +0300 (IDT) From: Avi Kivity To: Anthony Liguori , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org Subject: [PATCH v2 16/24] sh_pci: convert to memory API Date: Mon, 15 Aug 2011 17:17:30 +0300 Message-Id: <1313417858-6454-17-git-send-email-avi@redhat.com> In-Reply-To: <1313417858-6454-1-git-send-email-avi@redhat.com> References: <1313417858-6454-1-git-send-email-avi@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 15 Aug 2011 14:18:36 +0000 (UTC) Signed-off-by: Avi Kivity --- hw/sh_pci.c | 63 +++++++++++++++++++++++++++++++++++++++------------------- 1 files changed, 42 insertions(+), 21 deletions(-) diff --git a/hw/sh_pci.c b/hw/sh_pci.c index cd86501..76061bb 100644 --- a/hw/sh_pci.c +++ b/hw/sh_pci.c @@ -33,13 +33,16 @@ typedef struct SHPCIState { PCIBus *bus; PCIDevice *dev; qemu_irq irq[4]; - int memconfig; + MemoryRegion memconfig_p4; + MemoryRegion memconfig_a7; + MemoryRegion isa; uint32_t par; uint32_t mbr; uint32_t iobr; } SHPCIState; -static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val, + unsigned size) { SHPCIState *pcic = p; switch(addr) { @@ -54,10 +57,10 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) break; case 0x1c8: if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { - cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &pcic->isa); pcic->iobr = val & 0xfffc0001; - isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); + memory_region_add_subregion(get_system_memory(), + pcic->iobr & 0xfffc0000, &pcic->isa); } break; case 0x220: @@ -66,7 +69,8 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) } } -static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) +static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr, + unsigned size) { SHPCIState *pcic = p; switch(addr) { @@ -84,14 +88,14 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) return 0; } -typedef struct { - CPUReadMemoryFunc * const r[3]; - CPUWriteMemoryFunc * const w[3]; -} MemOp; - -static MemOp sh_pci_reg = { - { NULL, NULL, sh_pci_reg_read }, - { NULL, NULL, sh_pci_reg_write }, +static const MemoryRegionOps sh_pci_reg_ops = { + .read = sh_pci_reg_read, + .write = sh_pci_reg_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static int sh_pci_map_irq(PCIDevice *d, int irq_num) @@ -110,11 +114,23 @@ static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base) { SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); - cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig); - cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig); - + memory_region_add_subregion(get_system_memory(), + P4ADDR(base), + &s->memconfig_p4); + memory_region_add_subregion(get_system_memory(), + A7ADDR(base), + &s->memconfig_a7); s->iobr = 0xfe240000; - isa_mmio_init(s->iobr, 0x40000); + memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); +} + +static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) +{ + SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); + + memory_region_del_subregion(get_system_memory(), &s->memconfig_p4); + memory_region_del_subregion(get_system_memory(), &s->memconfig_a7); + memory_region_del_subregion(get_system_memory(), &s->isa); } static int sh_pci_init_device(SysBusDevice *dev) @@ -132,9 +148,14 @@ static int sh_pci_init_device(SysBusDevice *dev) get_system_memory(), get_system_io(), PCI_DEVFN(0, 0), 4); - s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, - s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio_cb(dev, 0x224, sh_pci_map); + memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s, + "sh_pci", 0x224); + memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_a7, + 0, 0x224); + isa_mmio_setup(&s->isa, 0x40000); + sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap); + sysbus_init_mmio_region(dev, &s->memconfig_a7); + sysbus_init_mmio_region(dev, &s->isa); s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host"); return 0; }