From patchwork Thu Jan 24 15:43:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2033531 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 8F73BE020A for ; Thu, 24 Jan 2013 16:12:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754687Ab3AXQMl (ORCPT ); Thu, 24 Jan 2013 11:12:41 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:58453 "EHLO mnementh.archaic.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752908Ab3AXQMa (ORCPT ); Thu, 24 Jan 2013 11:12:30 -0500 X-Greylist: delayed 1700 seconds by postgrey-1.27 at vger.kernel.org; Thu, 24 Jan 2013 11:12:29 EST Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TyOy9-0002zn-1S; Thu, 24 Jan 2013 15:44:01 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, kvm@vger.kernel.org, Marcelo Tosatti , kvmarm@lists.cs.columbia.edu, Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Gleb Natapov Subject: [RFC v5 5/8] hw/arm_gic: Add presave/postload hooks Date: Thu, 24 Jan 2013 15:43:57 +0000 Message-Id: <1359042240-11482-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1359042240-11482-1-git-send-email-peter.maydell@linaro.org> References: <1359042240-11482-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add presave/postload hooks to the ARM GIC common base class. These will be used by the KVM in-kernel GIC subclass to sync state between kernel and userspace when migrating. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- hw/arm_gic_common.c | 10 ++++++++++ hw/arm_gic_internal.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 40e8dd7..2947622 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -23,9 +23,14 @@ static void gic_save(QEMUFile *f, void *opaque) { GICState *s = (GICState *)opaque; + ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); int i; int j; + if (c->pre_save) { + c->pre_save(s); + } + qemu_put_be32(f, s->enabled); for (i = 0; i < s->num_cpu; i++) { qemu_put_be32(f, s->cpu_enabled[i]); @@ -57,6 +62,7 @@ static void gic_save(QEMUFile *f, void *opaque) static int gic_load(QEMUFile *f, void *opaque, int version_id) { GICState *s = (GICState *)opaque; + ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); int i; int j; @@ -91,6 +97,10 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) s->irq_state[i].trigger = qemu_get_byte(f); } + if (c->post_load) { + c->post_load(s); + } + return 0; } diff --git a/hw/arm_gic_internal.h b/hw/arm_gic_internal.h index 699352c..3640be0 100644 --- a/hw/arm_gic_internal.h +++ b/hw/arm_gic_internal.h @@ -118,6 +118,8 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq); typedef struct ARMGICCommonClass { SysBusDeviceClass parent_class; + void (*pre_save)(GICState *s); + void (*post_load)(GICState *s); } ARMGICCommonClass; #define TYPE_ARM_GIC "arm_gic"