From patchwork Fri Apr 26 06:43:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nakajima, Jun" X-Patchwork-Id: 2491061 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 6E4AA3FC64 for ; Fri, 26 Apr 2013 06:43:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759452Ab3DZGno (ORCPT ); Fri, 26 Apr 2013 02:43:44 -0400 Received: from mail-pb0-f54.google.com ([209.85.160.54]:49284 "EHLO mail-pb0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753605Ab3DZGnn (ORCPT ); Fri, 26 Apr 2013 02:43:43 -0400 Received: by mail-pb0-f54.google.com with SMTP id jt11so1047387pbb.27 for ; Thu, 25 Apr 2013 23:43:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=Rm7yJWq7zU3+anZctMJ2ntYCCYUtwRz/cGeCgsjjTwk=; b=AzFOmvNKUE70KTnW4VX53eMeXm5pr1UQI8ygQ+KBQ343X8dkAoZ+MSJKlgjWSM3x4w PM/3/OjFNj5532sax/nXbg3IU9UjdVfKxMMqHXfmBx5/X1IfNBfEIQYHex/xYWOwqosw sAryBEmCbu1+CA2L7/30HEctgTx6WT1R/pTVHYUKRzS6J5bI5C2LyyEVjokgdUPNHJpi xqou2sarJ/6ZRBJyQuGlIFKR02wPzPg99ielTOiAlNYnm6j0NYpzS3lprVZ7QBWuXvUY TKHvqzz8M5yAocGugVK+aL2WlkXzChdG//y6NNKTSQTQBbpu/VqWjGJQsi8QP7Z78890 wPQw== X-Received: by 10.68.36.230 with SMTP id t6mr57776085pbj.218.1366958622937; Thu, 25 Apr 2013 23:43:42 -0700 (PDT) Received: from localhost (c-98-207-34-191.hsd1.ca.comcast.net. [98.207.34.191]) by mx.google.com with ESMTPSA id dg5sm10428715pbc.29.2013.04.25.23.43.41 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Apr 2013 23:43:41 -0700 (PDT) From: Jun Nakajima To: kvm@vger.kernel.org Subject: [PATCH 04/11] nEPT: Fix cr3 handling in nested exit and entry Date: Thu, 25 Apr 2013 23:43:24 -0700 Message-Id: <1366958611-6935-4-git-send-email-jun.nakajima@intel.com> X-Mailer: git-send-email 1.8.2.1.610.g562af5b In-Reply-To: <1366958611-6935-3-git-send-email-jun.nakajima@intel.com> References: <1366958611-6935-1-git-send-email-jun.nakajima@intel.com> <1366958611-6935-2-git-send-email-jun.nakajima@intel.com> <1366958611-6935-3-git-send-email-jun.nakajima@intel.com> X-Gm-Message-State: ALoCoQnVuY/kTIRD9QzDY9djjDUGQozRYZB8VjOqHMnbXguALDEUNumRm1fO+wZecr+SuvCqfRJ+ Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The existing code for handling cr3 and related VMCS fields during nested exit and entry wasn't correct in all cases: If L2 is allowed to control cr3 (and this is indeed the case in nested EPT), during nested exit we must copy the modified cr3 from vmcs02 to vmcs12, and we forgot to do so. This patch adds this copy. If L0 isn't controlling cr3 when running L2 (i.e., L0 is using EPT), and whoever does control cr3 (L1 or L2) is using PAE, the processor might have saved PDPTEs and we should also save them in vmcs12 (and restore later). Signed-off-by: Nadav Har'El Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu --- arch/x86/kvm/vmx.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 6ab53ca..26a1b6f 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -7163,10 +7163,26 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) vmx_set_cr4(vcpu, vmcs12->guest_cr4); vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); - /* shadow page tables on either EPT or shadow page tables */ + /* + * Note that kvm_set_cr3() and kvm_mmu_reset_context() will do the + * right thing, and set GUEST_CR3 and/or EPT_POINTER in all supported + * settings: 1. shadow page tables on shadow page tables, 2. shadow + * page tables on EPT, 3. EPT on EPT. + */ kvm_set_cr3(vcpu, vmcs12->guest_cr3); kvm_mmu_reset_context(vcpu); + /* + * Additionally, except when L0 is using shadow page tables, L1 or + * L2 control guest_cr3 for L2, so they may also have saved PDPTEs + */ + if (enable_ept) { + vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); + vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); + vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); + vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); + } + kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); } @@ -7398,6 +7414,25 @@ void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) vmcs12->guest_pending_dbg_exceptions = vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); + /* + * In some cases (usually, nested EPT), L2 is allowed to change its + * own CR3 without exiting. If it has changed it, we must keep it. + * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined + * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. + */ + if (enable_ept) + vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3); + /* + * Additionally, except when L0 is using shadow page tables, L1 or + * L2 control guest_cr3 for L2, so save their PDPTEs + */ + if (enable_ept) { + vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); + vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); + vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); + vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); + } + /* TODO: These cannot have changed unless we have MSR bitmaps and * the relevant bit asks not to trap the change */ vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);