| Message ID | 1368942460-15577-15-git-send-email-sanjayl@kymasys.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/mips/kvm/kvm_mips_int.h b/arch/mips/kvm/kvm_mips_int.h index 20da7d2..7eac28e 100644 --- a/arch/mips/kvm/kvm_mips_int.h +++ b/arch/mips/kvm/kvm_mips_int.h @@ -29,8 +29,13 @@ #define C_TI (_ULCAST_(1) << 30) +#ifdef CONFIG_KVM_MIPS_VZ +#define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (1) +#define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (1) +#else #define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (0) #define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (0) +#endif void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, uint32_t priority); void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, uint32_t priority);
- In Trap & Emulate the hypervisor maintains exception priority in order to comply with the priorities defined by the architecture. - In VZ mode, we just set all the pending exception bits, and let the processor deliver them to the guest in the expected priority order. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> --- arch/mips/kvm/kvm_mips_int.h | 5 +++++ 1 file changed, 5 insertions(+)