diff mbox

[v3,7/9] hw/mips: In KVM mode, inject IRQ2 (I/O) interupts via ioctls

Message ID 1394125778-18746-8-git-send-email-james.hogan@imgtec.com (mailing list archive)
State New, archived
Headers show

Commit Message

James Hogan March 6, 2014, 5:09 p.m. UTC 
From: Sanjay Lal <sanjayl@kymasys.com>

COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Cc: Andreas Färber <afaerber@suse.de>
---
Changes in v3:
 - Pass MIPSCPU to kvm_mips_set_[ipi_]interrupt (Andreas Färber).

Changes in v2:
 - Expand commit message
 - Remove #ifdef CONFIG_KVM since it's guarded by kvm_enabled() already
---
 hw/mips/mips_int.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Andreas Färber March 13, 2014, 9:30 p.m. UTC | #1 
Am 06.03.2014 18:09, schrieb James Hogan:
> From: Sanjay Lal <sanjayl@kymasys.com>
> 
> COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
> ioctls.
> 
> Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Andreas Färber <afaerber@suse.de>
> ---
> Changes in v3:
>  - Pass MIPSCPU to kvm_mips_set_[ipi_]interrupt (Andreas Färber).

Reviewed-by: Andreas Färber <afaerber@suse.de>

Thanks,
Andreas
diff mbox

Patch

diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 7dbd24d..d740046 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -23,6 +23,8 @@ 
 #include "hw/hw.h"
 #include "hw/mips/cpudevs.h"
 #include "cpu.h"
+#include "sysemu/kvm.h"
+#include "kvm_mips.h"
 
 static void cpu_mips_irq_request(void *opaque, int irq, int level)
 {
@@ -35,8 +37,17 @@  static void cpu_mips_irq_request(void *opaque, int irq, int level)
 
     if (level) {
         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
+
+        if (kvm_enabled() && irq == 2) {
+            kvm_mips_set_interrupt(cpu, irq, level);
+        }
+
     } else {
         env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
+
+        if (kvm_enabled() && irq == 2) {
+            kvm_mips_set_interrupt(cpu, irq, level);
+        }
     }
 
     if (env->CP0_Cause & CP0Ca_IP_mask) {