From patchwork Tue Jun 17 22:10:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 4371471 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 488319F79B for ; Tue, 17 Jun 2014 22:14:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6C6FC201B9 for ; Tue, 17 Jun 2014 22:14:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB2F7202F2 for ; Tue, 17 Jun 2014 22:14:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967093AbaFQWOg (ORCPT ); Tue, 17 Jun 2014 18:14:36 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:29798 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967052AbaFQWOM (ORCPT ); Tue, 17 Jun 2014 18:14:12 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id D91DBD8C752DE; Tue, 17 Jun 2014 23:14:03 +0100 (IST) Received: from KLMAIL02.kl.imgtec.org (192.168.5.97) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Tue, 17 Jun 2014 23:10:44 +0100 Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by klmail02.kl.imgtec.org (192.168.5.97) with Microsoft SMTP Server (TLS) id 14.3.181.6; Tue, 17 Jun 2014 23:10:44 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.101) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 17 Jun 2014 23:10:43 +0100 From: James Hogan To: CC: , Aurelien Jarno , Gleb Natapov , Paolo Bonzini , Sanjay Lal , James Hogan Subject: [PATCH v5 01/12] target-mips: Reset CPU timer consistently Date: Tue, 17 Jun 2014 23:10:26 +0100 Message-ID: <1403043037-1271-2-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1403043037-1271-1-git-send-email-james.hogan@imgtec.com> References: <1403043037-1271-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.101] Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is reset at machine initialisation, including starting the timeout. Both registers however are placed before mvp in CPUMIPSState so they will both be zeroed on reset by the memset in mips_cpu_reset() including soon after init. This doesn't take into account that the timer may be running, in which case env->CP0_Count will represent the delta against the VM clock and the timeout will need updating. At init time (cpu_mips_clock_init()), lets only create the timer. Setting Count = 1 and starting the timer (cpu_mips_store_count()) can be done at reset time from cpu_state_reset(), which is after the memset. There is also no need to set CP0_Compare = 0 as that is already handled by the memset. Note that a reset occurs from mips_cpu_realizefn() which is before the machine init callback has had a chance to set up the CPU interrupts and the CPU timer, so env->timer will be NULL. This case is handled explicitly in cpu_mips_store_count(), treating the timer as disabled (which will also be the right thing to do when KVM support is added). Reported-by: Paolo Bonzini Signed-off-by: James Hogan Cc: Aurelien Jarno --- Changes in v5: - New patch (Paolo Bonzini). --- hw/mips/cputimer.c | 9 ++++++--- target-mips/translate.c | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c index c8b4b000cd0e..6900a745c60c 100644 --- a/hw/mips/cputimer.c +++ b/hw/mips/cputimer.c @@ -85,7 +85,12 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env) void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) + /* + * This gets called from cpu_state_reset(), potentially before timer init. + * So env->timer may be NULL, which is also the case with KVM enabled so + * treat timer as disabled in that case. + */ + if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) env->CP0_Count = count; else { /* Store new count register */ @@ -142,6 +147,4 @@ static void mips_timer_cb (void *opaque) void cpu_mips_clock_init (CPUMIPSState *env) { env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env); - env->CP0_Compare = 0; - cpu_mips_store_count(env, 1); } diff --git a/target-mips/translate.c b/target-mips/translate.c index 2c4c80103d14..b63f30fc3a76 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -16091,6 +16091,8 @@ void cpu_state_reset(CPUMIPSState *env) /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + cpu_mips_store_count(env, 1); + if (env->CP0_Config3 & (1 << CP0C3_MT)) { int i;