From patchwork Fri Jun 27 22:49:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 4437991 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E9C719F319 for ; Fri, 27 Jun 2014 22:49:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EB4C3203AD for ; Fri, 27 Jun 2014 22:49:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9AF82038F for ; Fri, 27 Jun 2014 22:49:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753333AbaF0WtT (ORCPT ); Fri, 27 Jun 2014 18:49:19 -0400 Received: from mail-by2lp0239.outbound.protection.outlook.com ([207.46.163.239]:13197 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751835AbaF0WtS (ORCPT ); Fri, 27 Jun 2014 18:49:18 -0400 Received: from CH1PR03CA003.namprd03.prod.outlook.com (10.255.156.148) by BLUPR03MB504.namprd03.prod.outlook.com (10.141.80.28) with Microsoft SMTP Server (TLS) id 15.0.959.24; Fri, 27 Jun 2014 22:49:15 +0000 Received: from BN1AFFO11FD008.protection.gbl (10.255.156.132) by CH1PR03CA003.outlook.office365.com (10.255.156.148) with Microsoft SMTP Server (TLS) id 15.0.974.11 via Frontend Transport; Fri, 27 Jun 2014 22:49:14 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD008.mail.protection.outlook.com (10.58.52.68) with Microsoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport; Fri, 27 Jun 2014 22:49:14 +0000 Received: from fsr-fed1764-012.ea.freescale.net (fsr-fed1764-012-010171073213.ea.freescale.net [10.171.73.213]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s5RMnAoT008904; Fri, 27 Jun 2014 15:49:12 -0700 From: Mihai Caraman To: CC: , , Mihai Caraman Subject: [PATCH 1/5 v4] KVM: PPC: e500mc: Revert "add load inst fixup" Date: Sat, 28 Jun 2014 01:49:03 +0300 Message-ID: <1403909347-31622-2-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1403909347-31622-1-git-send-email-mihai.caraman@freescale.com> References: <1403909347-31622-1-git-send-email-mihai.caraman@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(102836001)(104016002)(80022001)(106466001)(105606002)(46102001)(50226001)(88136002)(95666004)(62966002)(4396001)(104166001)(64706001)(2351001)(107046002)(26826002)(20776003)(36756003)(92726001)(47776003)(6806004)(48376002)(93916002)(19580405001)(19580395003)(50466002)(85852003)(33646001)(89996001)(81342001)(44976005)(85306003)(81542001)(83322001)(77156001)(31966008)(77982001)(87936001)(84676001)(79102001)(68736004)(74662001)(97736001)(87286001)(83072002)(76176999)(76482001)(21056001)(92566001)(50986999)(74502001)(99396002)(86362001)(229853001); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB504; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:ErrorRetry; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 0255DF69B9 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=mihai.caraman@freescale.com; X-OriginatorOrg: freescale.com Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The commit 1d628af7 "add load inst fixup" made an attempt to handle failures generated by reading the guest current instruction. The fixup code that was added works by chance hiding the real issue. Load external pid (lwepx) instruction, used by KVM to read guest instructions, is executed in a subsituted guest translation context (EPLC[EGS] = 1). In consequence lwepx's TLB error and data storage interrupts need to be handled by KVM, even though these interrupts are generated from host context (MSR[GS] = 0) where lwepx is executed. Currently, KVM hooks only interrupts generated from guest context (MSR[GS] = 1), doing minimal checks on the fast path to avoid host performance degradation. As a result, the host kernel handles lwepx faults searching the faulting guest data address (loaded in DEAR) in its own Logical Partition ID (LPID) 0 context. In case a host translation is found the execution returns to the lwepx instruction instead of the fixup, the host ending up in an infinite loop. Revert the commit "add load inst fixup". lwepx issue will be addressed in a subsequent patch without needing fixup code. Signed-off-by: Mihai Caraman --- v4-v2: - no change arch/powerpc/kvm/bookehv_interrupts.S | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index a1712b8..6ff4480 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -29,7 +29,6 @@ #include #include #include -#include #ifdef CONFIG_64BIT #include @@ -164,32 +163,9 @@ PPC_STL r30, VCPU_GPR(R30)(r4) PPC_STL r31, VCPU_GPR(R31)(r4) mtspr SPRN_EPLC, r8 - - /* disable preemption, so we are sure we hit the fixup handler */ - CURRENT_THREAD_INFO(r8, r1) - li r7, 1 - stw r7, TI_PREEMPT(r8) - isync - - /* - * In case the read goes wrong, we catch it and write an invalid value - * in LAST_INST instead. - */ -1: lwepx r9, 0, r5 -2: -.section .fixup, "ax" -3: li r9, KVM_INST_FETCH_FAILED - b 2b -.previous -.section __ex_table,"a" - PPC_LONG_ALIGN - PPC_LONG 1b,3b -.previous - + lwepx r9, 0, r5 mtspr SPRN_EPLC, r3 - li r7, 0 - stw r7, TI_PREEMPT(r8) stw r9, VCPU_LAST_INST(r4) .endif