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CY1PR0301MB1274; 5:1BjRJKY7ZevfzWUwIckjR00SUhImLutCCBmRQ9GQEbppEEFlXxZWF+CdbSvn0CN8pqFcRvAS3Qg2UnX8ng4a5H2/HXYPJ4VPpHlQK52IcupSLdOEbJbzpObN9JpBMONOJb3H2JdIPb03/tQ5rUEC5A==; 24:TtGu3v+zCKQsRs8oAxDBSpVLLZlS87HJHs96SOGNNG3iAKLnF7cXE+ilj6n2En9oCkQUulcEF0ndzBqaXT4ci9B+PVg7u5A2MOoyAxIASHc=; 20:9u061KaNiKrjkyukVEIy3rH89m+JnAHDleljHaws0pNJ9ZTHVVDePx9dKwmbIG6mDbttxFkR7tw/4Q9QXp4jyQ== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2015 09:23:21.7705 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1274 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-3.9 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_03_06, RCVD_IN_DNSWL_HI,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This APIs return the capability of automatically mapping msi-pages in iommu with some magic iova. Which is what currently most of iommu's does and is the default behaviour. Further API returns whether iommu allows the user to define different iova for mai-page mapping for the domain. This is required when a msi capable device is directly assigned to user-space/VM and user-space/VM need to define a non-overlapping (from other dma-able address space) iova for msi-pages mapping in iommu. This patch just define the interface and follow up patches will extend this interface. Signed-off-by: Bharat Bhushan --- drivers/iommu/arm-smmu.c | 3 +++ drivers/iommu/fsl_pamu_domain.c | 3 +++ drivers/iommu/iommu.c | 14 ++++++++++++++ include/linux/iommu.h | 9 ++++++++- 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 66a803b..a3956fb 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1406,6 +1406,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain, case DOMAIN_ATTR_NESTING: *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); return 0; + case DOMAIN_ATTR_MSI_MAPPING: + /* Dummy handling added */ + return 0; default: return -ENODEV; } diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index 1d45293..9a94430 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -856,6 +856,9 @@ static int fsl_pamu_get_domain_attr(struct iommu_domain *domain, case DOMAIN_ATTR_FSL_PAMUV1: *(int *)data = DOMAIN_ATTR_FSL_PAMUV1; break; + case DOMAIN_ATTR_MSI_MAPPING: + /* Dummy handling added */ + break; default: pr_debug("Unsupported attribute type\n"); ret = -EINVAL; diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d4f527e..16c2eab 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1216,6 +1216,7 @@ int iommu_domain_get_attr(struct iommu_domain *domain, bool *paging; int ret = 0; u32 *count; + struct iommu_domain_msi_maps *msi_maps; switch (attr) { case DOMAIN_ATTR_GEOMETRY: @@ -1236,6 +1237,19 @@ int iommu_domain_get_attr(struct iommu_domain *domain, ret = -ENODEV; break; + case DOMAIN_ATTR_MSI_MAPPING: + msi_maps = data; + + /* Default MSI-pages are magically mapped with some iova and + * do now allow to configure with different iova. + */ + msi_maps->automap = true; + msi_maps->override_automap = false; + + if (domain->ops->domain_get_attr) + ret = domain->ops->domain_get_attr(domain, attr, data); + + break; default: if (!domain->ops->domain_get_attr) return -EINVAL; diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 0546b87..6d49f3f 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -83,6 +83,13 @@ struct iommu_domain { struct iommu_domain_geometry geometry; }; +struct iommu_domain_msi_maps { + dma_addr_t base_address; + dma_addr_t size; + bool automap; + bool override_automap; +}; + enum iommu_cap { IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA transactions */ @@ -111,6 +118,7 @@ enum iommu_attr { DOMAIN_ATTR_FSL_PAMU_ENABLE, DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_NESTING, /* two stages of translation */ + DOMAIN_ATTR_MSI_MAPPING, /* Provides MSIs mapping in iommu */ DOMAIN_ATTR_MAX, }; @@ -167,7 +175,6 @@ struct iommu_ops { int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count); /* Get the numer of window per domain */ u32 (*domain_get_windows)(struct iommu_domain *domain); - #ifdef CONFIG_OF_IOMMU int (*of_xlate)(struct device *dev, struct of_phandle_args *args); #endif