From patchwork Tue Oct 6 17:49:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 7338871 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 863709F1D5 for ; Tue, 6 Oct 2015 17:50:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8BB6C205F5 for ; Tue, 6 Oct 2015 17:50:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89A2820715 for ; Tue, 6 Oct 2015 17:50:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752161AbbJFRuL (ORCPT ); Tue, 6 Oct 2015 13:50:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:39314 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752166AbbJFRuK (ORCPT ); Tue, 6 Oct 2015 13:50:10 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id BD6551418EC; Tue, 6 Oct 2015 17:50:09 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id A6DDF1418E8; Tue, 6 Oct 2015 17:50:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from keeshans.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 062021418E8; Tue, 6 Oct 2015 17:50:07 +0000 (UTC) From: Christopher Covington To: drjones@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, wei@redhat.com Cc: shannon.zhao@linaro.org, alistair.francis@xilinx.com, croberts@codeaurora.org, alindsay@codeaurora.org, Christopher Covington Subject: [kvm-unit-tests PATCHv3 3/3] arm: pmu: Add CPI checking Date: Tue, 6 Oct 2015 13:49:26 -0400 Message-Id: <1444153766-12532-4-git-send-email-cov@codeaurora.org> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1444153766-12532-1-git-send-email-cov@codeaurora.org> References: <5612EDA5.9010506@redhat.com> <1444153766-12532-1-git-send-email-cov@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Check the numbers of cycles per instruction (CPI) implied by ARM PMU cycle counter values. Check that in -icount mode these strictly match the specified rate. Signed-off-by: Christopher Covington --- arm/pmu.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- arm/unittests.cfg | 13 ++++++++++ 2 files changed, 84 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index 589e605..0ad113d 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -84,12 +84,82 @@ static bool check_cycles_increase(void) return true; } -int main(void) +/* Execute a known number of guest instructions. Only odd instruction counts + * greater than or equal to 3 are supported by the in-line assembly code. The + * control register (PMCR_EL0) is initialized with the provided value (allowing + * for example for the cycle counter or event counters to be reset). At the end + * of the exact instruction loop, zero is written to PMCR_EL0 to disable + * counting, allowing the cycle counter or event counters to be read at the + * leisure of the calling code. + */ +static void measure_instrs(int num, struct pmu_data pmcr) +{ + int i = (num - 1) / 2; + + if (num < 3 || ((num - 1) % 2)) + abort(); + + asm volatile( + "msr pmcr_el0, %[pmcr]\n" + "1: subs %[i], %[i], #1\n" + "b.gt 1b\n" + "msr pmcr_el0, xzr" + : [i] "+r" (i) : [pmcr] "r" (pmcr) : "cc"); +} + +/* Measure cycle counts for various known instruction counts. Ensure that the + * cycle counter progresses (similar to check_cycles_increase() but with more + * instructions and using reset and stop controls). If supplied a positive, + * nonzero CPI parameter, also strictly check that every measurement matches + * it. Strict CPI checking is used to test -icount mode. + */ +static bool check_cpi(int cpi) +{ + struct pmu_data pmcr; + + pmcr.cycle_counter_reset = 1; + pmcr.enable = 1; + + if (cpi > 0) + printf("Checking for CPI=%d.\n", cpi); + printf("instrs : cycles0 cycles1 ...\n"); + + for (int i = 3; i < 300; i += 32) { + int avg, sum = 0; + + printf("%d :", i); + for (int j = 0; j < samples; j++) { + int cycles; + + measure_instrs(i, pmcr); + asm volatile("mrs %0, pmccntr_el0" : "=r" (cycles)); + printf(" %d", cycles); + + if (!cycles || (cpi > 0 && cycles != i * cpi)) { + printf("\n"); + return false; + } + + sum += cycles; + } + avg = sum / samples; + printf(" sum=%d avg=%d avg_ipc=%d avg_cpi=%d\n", + sum, avg, i / avg, avg / i); + } + + return true; +} + +int main(int argc, char *argv[]) { report_prefix_push("pmu"); report("Control register", check_pmcr()); report("Monotonically increasing cycle count", check_cycles_increase()); + int cpi = (argc == 1 ? atol(argv[0]) : 0); + + report("Cycle/instruction ratio", check_cpi(cpi)); + return report_summary(); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index fd94adb..333ee0d 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -39,4 +39,17 @@ groups = selftest # Test PMU support without -icount [pmu] file = pmu.flat +extra_params = -append '-1' +groups = pmu + +# Test PMU support with -icount IPC=1 +[pmu-icount-1] +file = pmu.flat +extra_params = -icount 0 -append '1' +groups = pmu + +# Test PMU support with -icount IPC=256 +[pmu-icount-256] +file = pmu.flat +extra_params = -icount 8 -append '256' groups = pmu