From patchwork Tue Oct 20 07:22:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 7442421 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E30609F506 for ; Tue, 20 Oct 2015 07:23:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F07F4205E3 for ; Tue, 20 Oct 2015 07:23:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F34EC205E9 for ; Tue, 20 Oct 2015 07:23:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752761AbbJTHXm (ORCPT ); Tue, 20 Oct 2015 03:23:42 -0400 Received: from mga01.intel.com ([192.55.52.88]:17488 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752284AbbJTHXj (ORCPT ); Tue, 20 Oct 2015 03:23:39 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 20 Oct 2015 00:23:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,706,1437462000"; d="scan'208";a="815005596" Received: from hzzhang-optiplex-9020.sh.intel.com (HELO localhost) ([10.239.12.28]) by fmsmga001.fm.intel.com with ESMTP; 20 Oct 2015 00:23:37 -0700 From: Haozhong Zhang To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S. Tsirkin" , afaerber@suse.de, Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcelo Tosatti , Haozhong Zhang Subject: [PATCH v2 1/3] target-i386: add a subsection for migrating vcpu's TSC rate Date: Tue, 20 Oct 2015 15:22:52 +0800 Message-Id: <1445325774-7195-2-git-send-email-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.4.8 In-Reply-To: <1445325774-7195-1-git-send-email-haozhong.zhang@intel.com> References: <1445325774-7195-1-git-send-email-haozhong.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The newly added subsection 'vmstate_tsc_khz' is used by following patches to migrate vcpu's TSC rate. For the back migration compatibility, this subsection is not migrated on pc-*-2.4 and older machine types by default. If users do want to migrate this subsection on older machine types, they can enable it by giving a new cpu option 'save-tsc-freq'. Signed-off-by: Haozhong Zhang --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 1 + target-i386/cpu.h | 2 ++ target-i386/machine.c | 19 +++++++++++++++++++ 4 files changed, 27 insertions(+) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 0503485..7fde50f 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -300,6 +300,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_4 \ HW_COMPAT_2_4 \ {\ + .driver = TYPE_X86_CPU,\ + .property = "save-tsc-freq",\ + .value = "off",\ + },\ + {\ .driver = "Haswell-" TYPE_X86_CPU,\ .property = "abm",\ .value = "off",\ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 05d7f26..b6bb457 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3143,6 +3143,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), + DEFINE_PROP_BOOL("save-tsc-freq", X86CPU, env.save_tsc_khz, true), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0), DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 54d9d50..ba1a289 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -966,6 +966,8 @@ typedef struct CPUX86State { uint32_t sipi_vector; bool tsc_valid; int64_t tsc_khz; + int64_t tsc_khz_incoming; + bool save_tsc_khz; void *kvm_xsave_buf; uint64_t mcg_cap; diff --git a/target-i386/machine.c b/target-i386/machine.c index 9fa0563..7d68d63 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -752,6 +752,24 @@ static const VMStateDescription vmstate_xss = { } }; +static bool tsc_khz_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + return env->tsc_khz_incoming && env->save_tsc_khz; +} + +static const VMStateDescription vmstate_tsc_khz = { + .name = "cpu/tsc_khz", + .version_id = 1, + .minimum_version_id = 1, + .needed = tsc_khz_needed, + .fields = (VMStateField[]) { + VMSTATE_INT64(env.tsc_khz_incoming, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -871,6 +889,7 @@ VMStateDescription vmstate_x86_cpu = { &vmstate_msr_hyperv_crash, &vmstate_avx512, &vmstate_xss, + &vmstate_tsc_khz, NULL } };