From patchwork Fri Oct 30 06:22:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 7524331 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 78E199F71A for ; Fri, 30 Oct 2015 06:23:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6C54B20849 for ; Fri, 30 Oct 2015 06:23:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3BD4D20823 for ; Fri, 30 Oct 2015 06:23:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758651AbbJ3GXu (ORCPT ); Fri, 30 Oct 2015 02:23:50 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:4965 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758526AbbJ3GXs (ORCPT ); Fri, 30 Oct 2015 02:23:48 -0400 Received: from 172.24.1.47 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CVJ31651; Fri, 30 Oct 2015 14:23:10 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Fri, 30 Oct 2015 14:23:01 +0800 From: Shannon Zhao To: CC: , , , , , , , , , , Subject: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing Date: Fri, 30 Oct 2015 14:22:00 +0800 Message-ID: <1446186123-11548-19-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com> References: <1446186123-11548-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c | 4 +++ include/kvm/arm_pmu.h | 4 +++ virt/kvm/arm/pmu.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 83 insertions(+), 1 deletion(-) diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 78b2869..9c0fec4 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -28,6 +28,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" @@ -551,6 +552,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) { local_irq_enable(); + kvm_pmu_sync_hwstate(vcpu); kvm_vgic_sync_hwstate(vcpu); preempt_enable(); kvm_timer_sync_hwstate(vcpu); @@ -598,6 +600,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) kvm_guest_exit(); trace_kvm_exit(kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu)); + kvm_pmu_post_sync_hwstate(vcpu); + kvm_vgic_sync_hwstate(vcpu); preempt_enable(); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index acd025a..5e7f943 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -39,6 +39,8 @@ struct kvm_pmu { }; #ifdef CONFIG_KVM_ARM_PMU +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu); +void kvm_pmu_post_sync_hwstate(struct kvm_vcpu *vcpu); unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx); void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable); @@ -49,6 +51,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val); #else +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {} +void kvm_pmu_post_sync_hwstate(struct kvm_vcpu *vcpu) {} unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) { return 0; diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 11d1bfb..6d48d9a 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -21,6 +21,7 @@ #include #include #include +#include /** * kvm_pmu_get_counter_value - get PMU counter value @@ -69,6 +70,78 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc) } /** + * kvm_pmu_sync_hwstate - sync pmu state for cpu + * @vcpu: The vcpu pointer + * + * Inject virtual PMU IRQ if IRQ is pending for this cpu. + */ +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = &vcpu->arch.pmu; + u32 overflow; + + if (!vcpu_mode_is_32bit(vcpu)) + overflow = vcpu_sys_reg(vcpu, PMOVSSET_EL0); + else + overflow = vcpu_cp15(vcpu, c9_PMOVSSET); + + if ((pmu->irq_pending || overflow != 0) && (pmu->irq_num != -1)) + kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num, 1); + + pmu->irq_pending = false; +} + +/** + * kvm_pmu_post_sync_hwstate - post sync pmu state for cpu + * @vcpu: The vcpu pointer + * + * Inject virtual PMU IRQ if IRQ is pending for this cpu when back from guest. + */ +void kvm_pmu_post_sync_hwstate(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = &vcpu->arch.pmu; + + if (pmu->irq_pending && (pmu->irq_num != -1)) + kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num, 1); + + pmu->irq_pending = false; +} + +/** + * When perf event overflows, set irq_pending and call kvm_vcpu_kick() to inject + * the interrupt. + */ +static void kvm_pmu_perf_overflow(struct perf_event *perf_event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct kvm_pmc *pmc = perf_event->overflow_handler_context; + struct kvm_vcpu *vcpu = pmc->vcpu; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + int idx = pmc->idx; + + if (!vcpu_mode_is_32bit(vcpu)) { + if ((vcpu_sys_reg(vcpu, PMINTENSET_EL1) >> idx) & 0x1) { + __set_bit(idx, + (unsigned long *)&vcpu_sys_reg(vcpu, PMOVSSET_EL0)); + __set_bit(idx, + (unsigned long *)&vcpu_sys_reg(vcpu, PMOVSCLR_EL0)); + pmu->irq_pending = true; + kvm_vcpu_kick(vcpu); + } + } else { + if ((vcpu_cp15(vcpu, c9_PMINTENSET) >> idx) & 0x1) { + __set_bit(idx, + (unsigned long *)&vcpu_cp15(vcpu, c9_PMOVSSET)); + __set_bit(idx, + (unsigned long *)&vcpu_cp15(vcpu, c9_PMOVSCLR)); + pmu->irq_pending = true; + kvm_vcpu_kick(vcpu); + } + } +} + +/** * kvm_pmu_enable_counter - enable selected PMU counter * @vcpu: The vcpu pointer * @val: the value guest writes to PMCNTENSET register @@ -293,7 +366,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, /* The initial sample period (overflow count) of an event. */ attr.sample_period = (-counter) & pmc->bitmask; - event = perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc); + event = perf_event_create_kernel_counter(&attr, -1, current, + kvm_pmu_perf_overflow, pmc); if (IS_ERR(event)) { printk_once("kvm: pmu event creation failed %ld\n", PTR_ERR(event));