From patchwork Wed Dec 16 23:49:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 7866841 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D076DBEEE5 for ; Wed, 16 Dec 2015 23:50:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6AF5202BE for ; Wed, 16 Dec 2015 23:50:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0D14E202B8 for ; Wed, 16 Dec 2015 23:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965466AbbLPXuP (ORCPT ); Wed, 16 Dec 2015 18:50:15 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:7514 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934370AbbLPXuN (ORCPT ); Wed, 16 Dec 2015 18:50:13 -0500 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id 8962E1E41BC20; Wed, 16 Dec 2015 23:50:07 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.235.1; Wed, 16 Dec 2015 23:50:11 +0000 Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 16 Dec 2015 23:50:10 +0000 From: James Hogan To: Ralf Baechle , Paolo Bonzini CC: Gleb Natapov , , , James Hogan Subject: [PATCH 12/16] MIPS: KVM: Use cacheops.h definitions Date: Wed, 16 Dec 2015 23:49:37 +0000 Message-ID: <1450309781-28030-13-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.4.10 In-Reply-To: <1450309781-28030-1-git-send-email-james.hogan@imgtec.com> References: <1450309781-28030-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Drop the custom cache operation code definitions used by KVM for emulating guest CACHE instructions, and switch to use the existing definitions in . Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: Gleb Natapov Cc: Ralf Baechle Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org --- arch/mips/kvm/emulate.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index 6ff1dcfc9ef1..0eb65668d2ab 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -1544,19 +1545,6 @@ int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu *vcpu) return 0; } -#define MIPS_CACHE_OP_INDEX_INV 0x0 -#define MIPS_CACHE_OP_INDEX_LD_TAG 0x1 -#define MIPS_CACHE_OP_INDEX_ST_TAG 0x2 -#define MIPS_CACHE_OP_IMP 0x3 -#define MIPS_CACHE_OP_HIT_INV 0x4 -#define MIPS_CACHE_OP_FILL_WB_INV 0x5 -#define MIPS_CACHE_OP_HIT_HB 0x6 -#define MIPS_CACHE_OP_FETCH_LOCK 0x7 - -#define MIPS_CACHE_ICACHE 0x0 -#define MIPS_CACHE_DCACHE 0x1 -#define MIPS_CACHE_SEC 0x3 - enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc, uint32_t cause, struct kvm_run *run, @@ -1581,8 +1569,8 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc, base = (inst >> 21) & 0x1f; op_inst = (inst >> 16) & 0x1f; offset = (int16_t)inst; - cache = (inst >> 16) & 0x3; - op = (inst >> 18) & 0x7; + cache = op_inst & CacheOp_Cache; + op = op_inst & CacheOp_Op; va = arch->gprs[base] + offset; @@ -1594,14 +1582,14 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc, * invalidate the caches entirely by stepping through all the * ways/indexes */ - if (op == MIPS_CACHE_OP_INDEX_INV) { + if (op == Index_Writeback_Inv) { kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, arch->gprs[base], offset); - if (cache == MIPS_CACHE_DCACHE) + if (cache == Cache_D) r4k_blast_dcache(); - else if (cache == MIPS_CACHE_ICACHE) + else if (cache == Cache_I) r4k_blast_icache(); else { kvm_err("%s: unsupported CACHE INDEX operation\n", @@ -1674,9 +1662,7 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc, skip_fault: /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */ - if (cache == MIPS_CACHE_DCACHE - && (op == MIPS_CACHE_OP_FILL_WB_INV - || op == MIPS_CACHE_OP_HIT_INV)) { + if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) { flush_dcache_line(va); #ifdef CONFIG_KVM_MIPS_DYN_TRANS @@ -1686,7 +1672,7 @@ skip_fault: */ kvm_mips_trans_cache_va(inst, opc, vcpu); #endif - } else if (op == MIPS_CACHE_OP_HIT_INV && cache == MIPS_CACHE_ICACHE) { + } else if (op_inst == Hit_Invalidate_I) { flush_dcache_line(va); flush_icache_line(va);