From patchwork Tue Mar 1 22:34:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Feiner X-Patchwork-Id: 8471081 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E52F7C0553 for ; Tue, 1 Mar 2016 22:35:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EE18E20304 for ; Tue, 1 Mar 2016 22:35:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8313B20357 for ; Tue, 1 Mar 2016 22:35:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751406AbcCAWfK (ORCPT ); Tue, 1 Mar 2016 17:35:10 -0500 Received: from mail-pa0-f46.google.com ([209.85.220.46]:33805 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750862AbcCAWfJ (ORCPT ); Tue, 1 Mar 2016 17:35:09 -0500 Received: by mail-pa0-f46.google.com with SMTP id fy10so119674813pac.1 for ; Tue, 01 Mar 2016 14:35:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SSKJWm+Yqz/9R3QPWuu5HFi0Qv124GwZ/zvQpF+siW4=; b=T4CH5NSth+6hLQCNm5+HZIaIXJYAqJNrwjBDVro/FoF2sAUFnxPAf2VqplDNmF8bs6 Hr9gvF6QNyCzsHXsjN7GrTJMdbYa3vmSg03LcjXoQNTOVAAopK3emAkT3plhUhXK0hKZ 7PcoId9zzGuzen4aQrCrBETHtiajQMsi9kSKJJVdWom2eqXVF0PiY6DoD8dyjI8wdtKL bQw1oyLdUpg1k1GSX+uMdWgBlYPIJf6khrblfe+XWa98LQGPMBXeHaHvPJGZFBI291YU 4Wqfy8NGOOu/m9bctnCxbZQrQJ2vQWCRdQJoIs1q4VhX1y+c8Y0RUUZ5Fg/INcW+kiJK xM2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SSKJWm+Yqz/9R3QPWuu5HFi0Qv124GwZ/zvQpF+siW4=; b=Rsy4N5mrRokNEAEZKH+ANT+BcML3UqnUg6hfPWz3R+x8vrjTrqbVIb1rUvotts+GZv FiGVuzmlCvG2DGD5y7sr1OI4xWS9Yo6ftP+Z49att1NqULF7cl8Nfil/dihZZwgLBnxp LmezALkbh/i4k/nLpJG10g6uvYxF03rCJn3oCfG0BLPpyLUGfMHpiUxboNgio+s6KAog Kq/Z9WuTiBxONet0Flabpx/9X4q+i45lMx5AccZ+8a6KkL2LzIPrCSkMoZnDZnPzWeep BovLeiScSyq97qaOe18Y9dzO5KnuJGtmMsdcMjD+g1ZjvtOqmFcpVRAZRvDr9rCXCXmB rFgw== X-Gm-Message-State: AD7BkJI3ECmjd86WOZlvMsOzaoIpgHKncGqsaeoyYktPESCkP2M1PvsTkQj9XJhQosjngknC X-Received: by 10.66.155.232 with SMTP id vz8mr33916190pab.53.1456871708182; Tue, 01 Mar 2016 14:35:08 -0800 (PST) Received: from localhost ([2620:0:1009:3:b1e9:1d95:1ce5:e70c]) by smtp.gmail.com with ESMTPSA id cq4sm47872140pad.28.2016.03.01.14.35.07 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 01 Mar 2016 14:35:07 -0800 (PST) From: Peter Feiner To: kvm@vger.kernel.org, jan.kiszka@siemens.com, drjones@redhat.com, pbonzini@redhat.com Cc: pfeiner@google.com Subject: [kvm-unit-tests v2 1/6] x86: vmx.h: trivial whitespace fixes Date: Tue, 1 Mar 2016 14:34:49 -0800 Message-Id: <1456871694-23042-2-git-send-email-pfeiner@google.com> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: <1456871694-23042-1-git-send-email-pfeiner@google.com> References: <1456860622-31251-1-git-send-email-pfeiner@google.com> <1456871694-23042-1-git-send-email-pfeiner@google.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Peter Feiner --- x86/vmx.h | 107 +++++++++++++++++++++++++++++++------------------------------- 1 file changed, 53 insertions(+), 54 deletions(-) diff --git a/x86/vmx.h b/x86/vmx.h index f868e5d..8b79191 100644 --- a/x86/vmx.h +++ b/x86/vmx.h @@ -196,8 +196,8 @@ enum Encoding { /* Natural-Width Control Fields */ CR0_MASK = 0x6000ul, CR4_MASK = 0x6002ul, - CR0_READ_SHADOW = 0x6004ul, - CR4_READ_SHADOW = 0x6006ul, + CR0_READ_SHADOW = 0x6004ul, + CR4_READ_SHADOW = 0x6006ul, CR3_TARGET_0 = 0x6008ul, CR3_TARGET_1 = 0x600aul, CR3_TARGET_2 = 0x600cul, @@ -304,27 +304,27 @@ enum Reason { enum Ctrl_exi { EXI_SAVE_DBGCTLS = 1UL << 2, - EXI_HOST_64 = 1UL << 9, + EXI_HOST_64 = 1UL << 9, EXI_LOAD_PERF = 1UL << 12, - EXI_INTA = 1UL << 15, + EXI_INTA = 1UL << 15, EXI_SAVE_PAT = 1UL << 18, EXI_LOAD_PAT = 1UL << 19, EXI_SAVE_EFER = 1UL << 20, - EXI_LOAD_EFER = 1UL << 21, + EXI_LOAD_EFER = 1UL << 21, EXI_SAVE_PREEMPT = 1UL << 22, }; enum Ctrl_ent { ENT_LOAD_DBGCTLS = 1UL << 2, - ENT_GUEST_64 = 1UL << 9, + ENT_GUEST_64 = 1UL << 9, ENT_LOAD_PAT = 1UL << 14, - ENT_LOAD_EFER = 1UL << 15, + ENT_LOAD_EFER = 1UL << 15, }; enum Ctrl_pin { - PIN_EXTINT = 1ul << 0, - PIN_NMI = 1ul << 3, - PIN_VIRT_NMI = 1ul << 5, + PIN_EXTINT = 1ul << 0, + PIN_NMI = 1ul << 3, + PIN_VIRT_NMI = 1ul << 5, PIN_PREEMPT = 1ul << 6, }; @@ -396,85 +396,85 @@ enum Ctrl1 { #define LOAD_GPR_C SAVE_GPR_C #define SAVE_RFLAGS \ - "pushf\n\t" \ + "pushf\n\t" \ "pop host_rflags\n\t" #define LOAD_RFLAGS \ "push host_rflags\n\t" \ "popf\n\t" -#define VMX_IO_SIZE_MASK 0x7 -#define _VMX_IO_BYTE 0 -#define _VMX_IO_WORD 1 -#define _VMX_IO_LONG 3 -#define VMX_IO_DIRECTION_MASK (1ul << 3) -#define VMX_IO_IN (1ul << 3) -#define VMX_IO_OUT 0 -#define VMX_IO_STRING (1ul << 4) -#define VMX_IO_REP (1ul << 5) -#define VMX_IO_OPRAND_IMM (1ul << 6) -#define VMX_IO_PORT_MASK 0xFFFF0000 -#define VMX_IO_PORT_SHIFT 16 - -#define VMX_TEST_START 0 -#define VMX_TEST_VMEXIT 1 -#define VMX_TEST_EXIT 2 -#define VMX_TEST_RESUME 3 -#define VMX_TEST_LAUNCH_ERR 4 -#define VMX_TEST_RESUME_ERR 5 +#define VMX_IO_SIZE_MASK 0x7 +#define _VMX_IO_BYTE 0 +#define _VMX_IO_WORD 1 +#define _VMX_IO_LONG 3 +#define VMX_IO_DIRECTION_MASK (1ul << 3) +#define VMX_IO_IN (1ul << 3) +#define VMX_IO_OUT 0 +#define VMX_IO_STRING (1ul << 4) +#define VMX_IO_REP (1ul << 5) +#define VMX_IO_OPRAND_IMM (1ul << 6) +#define VMX_IO_PORT_MASK 0xFFFF0000 +#define VMX_IO_PORT_SHIFT 16 + +#define VMX_TEST_START 0 +#define VMX_TEST_VMEXIT 1 +#define VMX_TEST_EXIT 2 +#define VMX_TEST_RESUME 3 +#define VMX_TEST_LAUNCH_ERR 4 +#define VMX_TEST_RESUME_ERR 5 #define HYPERCALL_BIT (1ul << 12) #define HYPERCALL_MASK 0xFFF #define HYPERCALL_VMEXIT 0x1 #define EPTP_PG_WALK_LEN_SHIFT 3ul -#define EPTP_AD_FLAG (1ul << 6) +#define EPTP_AD_FLAG (1ul << 6) -#define EPT_MEM_TYPE_UC 0ul -#define EPT_MEM_TYPE_WC 1ul -#define EPT_MEM_TYPE_WT 4ul -#define EPT_MEM_TYPE_WP 5ul -#define EPT_MEM_TYPE_WB 6ul +#define EPT_MEM_TYPE_UC 0ul +#define EPT_MEM_TYPE_WC 1ul +#define EPT_MEM_TYPE_WT 4ul +#define EPT_MEM_TYPE_WP 5ul +#define EPT_MEM_TYPE_WB 6ul #define EPT_RA 1ul #define EPT_WA 2ul #define EPT_EA 4ul -#define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) -#define EPT_ACCESS_FLAG (1ul << 8) +#define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) +#define EPT_ACCESS_FLAG (1ul << 8) #define EPT_DIRTY_FLAG (1ul << 9) #define EPT_LARGE_PAGE (1ul << 7) #define EPT_MEM_TYPE_SHIFT 3ul #define EPT_IGNORE_PAT (1ul << 6) -#define EPT_SUPPRESS_VE (1ull << 63) +#define EPT_SUPPRESS_VE (1ull << 63) #define EPT_CAP_WT 1ull #define EPT_CAP_PWL4 (1ull << 6) #define EPT_CAP_UC (1ull << 8) #define EPT_CAP_WB (1ull << 14) -#define EPT_CAP_2M_PAGE (1ull << 16) -#define EPT_CAP_1G_PAGE (1ull << 17) +#define EPT_CAP_2M_PAGE (1ull << 16) +#define EPT_CAP_1G_PAGE (1ull << 17) #define EPT_CAP_INVEPT (1ull << 20) #define EPT_CAP_INVEPT_SINGLE (1ull << 25) #define EPT_CAP_INVEPT_ALL (1ull << 26) -#define EPT_CAP_AD_FLAG (1ull << 21) -#define VPID_CAP_INVVPID (1ull << 32) -#define VPID_CAP_INVVPID_SINGLE (1ull << 41) -#define VPID_CAP_INVVPID_ALL (1ull << 42) +#define EPT_CAP_AD_FLAG (1ull << 21) +#define VPID_CAP_INVVPID (1ull << 32) +#define VPID_CAP_INVVPID_SINGLE (1ull << 41) +#define VPID_CAP_INVVPID_ALL (1ull << 42) #define PAGE_SIZE_2M (512 * PAGE_SIZE) #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) -#define EPT_PAGE_LEVEL 4 -#define EPT_PGDIR_WIDTH 9 -#define EPT_PGDIR_MASK 511 +#define EPT_PAGE_LEVEL 4 +#define EPT_PGDIR_WIDTH 9 +#define EPT_PGDIR_MASK 511 #define PAGE_MASK (~(PAGE_SIZE-1)) #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) #define EPT_VLT_RD 1 #define EPT_VLT_WR (1 << 1) #define EPT_VLT_FETCH (1 << 2) -#define EPT_VLT_PERM_RD (1 << 3) -#define EPT_VLT_PERM_WR (1 << 4) -#define EPT_VLT_PERM_EX (1 << 5) +#define EPT_VLT_PERM_RD (1 << 3) +#define EPT_VLT_PERM_WR (1 << 4) +#define EPT_VLT_PERM_EX (1 << 5) #define EPT_VLT_LADDR_VLD (1 << 7) #define EPT_VLT_PADDR (1 << 8) @@ -485,8 +485,8 @@ enum Ctrl1 { #define INVEPT_SINGLE 1 #define INVEPT_GLOBAL 2 -#define INVVPID_SINGLE 1 -#define INVVPID_ALL 2 +#define INVVPID_SINGLE 1 +#define INVVPID_ALL 2 #define ACTV_ACTIVE 0 #define ACTV_HLT 1 @@ -577,4 +577,3 @@ int set_ept_pte(unsigned long *pml4, unsigned long guest_addr, int level, u64 pte_val); #endif -