From patchwork Thu Apr 14 14:49:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 8838261 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6E7D2C0553 for ; Thu, 14 Apr 2016 14:49:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7CC0220272 for ; Thu, 14 Apr 2016 14:49:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 69C95201C7 for ; Thu, 14 Apr 2016 14:49:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753866AbcDNOtq (ORCPT ); Thu, 14 Apr 2016 10:49:46 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55655 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751436AbcDNOtp (ORCPT ); Thu, 14 Apr 2016 10:49:45 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4A9ED47048; Thu, 14 Apr 2016 14:49:45 +0000 (UTC) Received: from thh440s.fritz.box (vpn1-6-40.ams2.redhat.com [10.36.6.40]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u3EEnhwU009758; Thu, 14 Apr 2016 10:49:43 -0400 From: Thomas Huth To: kvm@vger.kernel.org, lvivier@redhat.com Cc: kvm-ppc@vger.kernel.org, pbonzini@redhat.com, drjones@redhat.com Subject: [kvm-unit-test PATCH v2] powerpc: Add emulator test for the lswi instruction Date: Thu, 14 Apr 2016 16:49:42 +0200 Message-Id: <1460645382-31616-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This test checks some special cases of the lswi instruction. Test works fine on real hardware, but in QEMU, this reveals a bug with the final "don't overwrite Ra" test (RA gets destroyed since the check in QEMU is still wrong). The code is based on the lswx test by Laurent Vivier. Signed-off-by: Thomas Huth Reviewed-by: Laurent Vivier --- v2: Do not clobber r2 during the final test, since it is needed by the exception handler powerpc/emulator.c | 124 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/powerpc/emulator.c b/powerpc/emulator.c index 3696d83..4dc341f 100644 --- a/powerpc/emulator.c +++ b/powerpc/emulator.c @@ -71,6 +71,129 @@ static void test_64bit(void) report_prefix_pop(); } +/** + * Test 'Load String Word Immediate' instruction + */ +static void test_lswi(void) +{ + int i; + char addr[128]; + uint64_t regs[32]; + + report_prefix_push("lswi"); + + /* fill memory with sequence */ + for (i = 0; i < 128; i++) + addr[i] = 1 + i; + + /* check incomplete register filling */ + alignment = 0; + asm volatile ("li r12,-1;" + "mr r11, r12;" + "lswi r11, %[addr], %[len];" + "std r11, 0*8(%[regs]);" + "std r12, 1*8(%[regs]);" + :: + [len] "i" (3), + [addr] "b" (addr), + [regs] "r" (regs) + : + "r11", "r12", "memory"); + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + /* + * lswi is supposed to cause an alignment exception in little endian + * mode, but QEMU does not support it. So in case we do not get an + * exception, this is an expected failure and we run the other tests + */ + report_xfail("alignment", !alignment, alignment); + if (alignment) { + report_prefix_pop(); + return; + } +#endif + report("partial", regs[0] == 0x01020300 && regs[1] == (uint64_t)-1); + + /* check NB = 0 ==> 32 bytes. */ + asm volatile ("li r19,-1;" + "mr r11, r19; mr r12, r19; mr r13, r19;" + "mr r14, r19; mr r15, r19; mr r16, r19;" + "mr r17, r19; mr r18, r19;" + "lswi r11, %[addr], %[len];" + "std r11, 0*8(%[regs]);" + "std r12, 1*8(%[regs]);" + "std r13, 2*8(%[regs]);" + "std r14, 3*8(%[regs]);" + "std r15, 4*8(%[regs]);" + "std r16, 5*8(%[regs]);" + "std r17, 6*8(%[regs]);" + "std r18, 7*8(%[regs]);" + "std r19, 8*8(%[regs]);" + :: + [len] "i" (0), + [addr] "b" (addr), + [regs] "r" (regs) + : + /* as 32 is the number of bytes, + * we should modify 32/4 = 8 regs, from r11 to r18 + * We check r19 is unmodified by filling it with 1s + * before the instruction. + */ + "r11", "r12", "r13", "r14", "r15", "r16", "r17", + "r18", "r19", "memory"); + + report("length", regs[0] == 0x01020304 && regs[1] == 0x05060708 && + regs[2] == 0x090a0b0c && regs[3] == 0x0d0e0f10 && + regs[4] == 0x11121314 && regs[5] == 0x15161718 && + regs[6] == 0x191a1b1c && regs[7] == 0x1d1e1f20 && + regs[8] == (uint64_t)-1); + + /* check wrap around to r0 */ + asm volatile ("li r31,-1;" + "mr r0, r31;" + "lswi r31, %[addr], %[len];" + "std r31, 0*8(%[regs]);" + "std r0, 1*8(%[regs]);" + :: + [len] "i" (8), + [addr] "b" (addr), + [regs] "r" (regs) + : + /* modify two registers from r31, wrap around to r0 */ + "r31", "r0", "memory"); + + report("wrap around to r0", regs[0] == 0x01020304 && + regs[1] == 0x05060708); + + /* check wrap around doesn't break RA */ + asm volatile ("mr r29,r1\n" + "li r31,-1\n" + "mr r0,r31\n" + "mr r1, %[addr]\n" + ".long 0x7fe154aa\n" /* lswi r31, r1, 10 */ + "std r31, 0*8(%[regs])\n" + "std r0, 1*8(%[regs])\n" + "std r1, 2*8(%[regs])\n" + "mr r1,r29\n" + :: + [addr] "r" (addr), + [regs] "r" (regs) + : + /* loading three registers from r31 wraps around to r1, + * r1 is saved to r29, as adding it to the clobber + * list doesn't protect it + */ + "r0", "r29", "r31", "memory"); + + /* doc says it is invalid, real proc stops when it comes to + * overwrite the register. + * In all the cases, the register must stay untouched + */ + report("Don't overwrite Ra", regs[2] == (uint64_t)addr); + + report_prefix_pop(); +} + /* * lswx: Load String Word Indexed X-form * @@ -235,6 +358,7 @@ int main(int argc, char **argv) test_64bit(); test_illegal(); test_lswx(); + test_lswi(); report_prefix_pop();