| Message ID | 1464847803-22756-2-git-send-email-xyjxie@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/include/linux/pci.h b/include/linux/pci.h index 932ec74..4ec37da 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -187,6 +187,7 @@ typedef unsigned short __bitwise pci_bus_flags_t; enum pci_bus_flags { PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, + PCI_BUS_FLAGS_MSI_REMAP = (__force pci_bus_flags_t) 4, }; /* These values come from the PCI Express Spec */
We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP which indicates interrupts of all devices on the bus are managed by the hardware enabling IRQ remapping(intel naming). When the capability is enabled, a given PCI device can only shoot the MSIs assigned for it. In other words, the hardware can protect system from invalid MSIs of the device by checking the target address and data when there is something wrong with MSI part in device or device driver. There is a existing flag for this capability in the IOMMU space: enum iommu_cap { IOMMU_CAP_CACHE_COHERENCY, ---> IOMMU_CAP_INTR_REMAP, IOMMU_CAP_NOEXEC, }; and Eric also posted a patchset [1] to abstract it on MSI controller side for ARM. But it would make sense to have a more common flag like PCI_BUS_FLAGS_MSI_REMAP so that we can use a universal flag to test this capability on PCI side for different archs. With this flag enabled, we can easily know whether it's safe to expose MSI-X tables of PCI BARs to userspace. Some usespace drivers such as VFIO may benefit from this. [1] https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg1138820.html Signed-off-by: Yongji Xie <xyjxie@linux.vnet.ibm.com> --- include/linux/pci.h | 1 + 1 file changed, 1 insertion(+)