From patchwork Mon Jan 9 06:24:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 9503817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 445A860757 for ; Mon, 9 Jan 2017 06:27:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35059280D0 for ; Mon, 9 Jan 2017 06:27:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 294DD2815E; Mon, 9 Jan 2017 06:27:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.4 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 888F1280D0 for ; Mon, 9 Jan 2017 06:27:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938291AbdAIG1G (ORCPT ); Mon, 9 Jan 2017 01:27:06 -0500 Received: from outprodmail01.cc.columbia.edu ([128.59.72.39]:38331 "EHLO outprodmail01.cc.columbia.edu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S939724AbdAIG0K (ORCPT ); Mon, 9 Jan 2017 01:26:10 -0500 Received: from hazelnut (hazelnut.cc.columbia.edu [128.59.213.250]) by outprodmail01.cc.columbia.edu (8.14.4/8.14.4) with ESMTP id v096Q5sB017972 for ; Mon, 9 Jan 2017 01:26:09 -0500 Received: from hazelnut (localhost.localdomain [127.0.0.1]) by hazelnut (Postfix) with ESMTP id 26A2A8B for ; Mon, 9 Jan 2017 01:26:09 -0500 (EST) Received: from sendprodmail03.cc.columbia.edu (sendprodmail03.cc.columbia.edu [128.59.72.15]) by hazelnut (Postfix) with ESMTP id 639FB8B for ; Mon, 9 Jan 2017 01:26:07 -0500 (EST) Received: from mail-qt0-f197.google.com (mail-qt0-f197.google.com [209.85.216.197]) by sendprodmail03.cc.columbia.edu (8.14.4/8.14.4) with ESMTP id v096Q7WD057218 (version=TLSv1/SSLv3 cipher=AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 9 Jan 2017 01:26:07 -0500 Received: by mail-qt0-f197.google.com with SMTP id l7so63077742qtd.2 for ; Sun, 08 Jan 2017 22:26:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8+dzRdseMot+xA5pZmeRZ0n7xSs1oaRlCmwiTXWHgp8=; b=hFXY6pdVtKHcs1w2tKthHV101LC+Dvn/7wMGK99uXNlNYFDhKWSd796/b7o+z53xNo gnmnxBW5wD0exU6GnHLrQtUffQW25BKuG136gHjENZoLgJcpXUkZbfAljE9XbkvrJhrh j3Q9UFYwiI73vbmyl2V4gPH1QiHnWnH/tdDu6II08RNeEDH0e2uCv4ZPOx0/IMz95hBy yCunzMqvpvP+tiR81hzMePML6vMlEXS4u+mH/3QjES+nKlLPBHU8pLehsoBO2BETByit HDv554C1tDLMcAfFT1Nb+QZDbxI9kYtcJ/r8GoOPYSZaSQ9B6GyYklMyH0bkYobwKTV+ elWQ== X-Gm-Message-State: AIkVDXKOMY0OTtC1W042EfXlIUqCX7J1+LLQMNu7DAUIV4d8phIIvTx3fGOdYLt2C7lsGURTCQh19COZY7a67e/rQSeAfRPN5t0kvQq/mdIGzZ82YNsdLVDR0ZWro2Tdc/+HXcOFFfVsqpE= X-Received: by 10.55.39.193 with SMTP id n184mr20779676qkn.315.1483943166936; Sun, 08 Jan 2017 22:26:06 -0800 (PST) X-Received: by 10.55.39.193 with SMTP id n184mr20779669qkn.315.1483943166709; Sun, 08 Jan 2017 22:26:06 -0800 (PST) Received: from jintack.cs.columbia.edu ([2001:18d8:ffff:16:21a:4aff:feaa:f900]) by smtp.gmail.com with ESMTPSA id h3sm8623257qtc.6.2017.01.08.22.26.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 08 Jan 2017 22:26:06 -0800 (PST) From: Jintack Lim To: christoffer.dall@linaro.org, marc.zyngier@arm.com, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, vladimir.murzin@arm.com, suzuki.poulose@arm.com, mark.rutland@arm.com, james.morse@arm.com, lorenzo.pieralisi@arm.com, kevin.brodsky@arm.com, wcohen@redhat.com, shankerd@codeaurora.org, geoff@infradead.org, andre.przywara@arm.com, eric.auger@redhat.com, anna-maria@linutronix.de, shihwei@cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jintack@cs.columbia.edu Subject: [RFC 27/55] KVM: arm/arm64: Emulate GICH interface on GICv2 Date: Mon, 9 Jan 2017 01:24:23 -0500 Message-Id: <1483943091-1364-28-git-send-email-jintack@cs.columbia.edu> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483943091-1364-1-git-send-email-jintack@cs.columbia.edu> References: <1483943091-1364-1-git-send-email-jintack@cs.columbia.edu> X-No-Spam-Score: Local X-Scanned-By: MIMEDefang 2.78 on 128.59.72.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Emulate GICH interface accesses from the guest hypervisor. Signed-off-by: Jintack Lim Signed-off-by: Shih-Wei Li Signed-off-by: Christoffer Dall --- arch/arm64/kvm/Makefile | 1 + virt/kvm/arm/vgic/vgic-v2-nested.c | 207 +++++++++++++++++++++++++++++++++++++ 2 files changed, 208 insertions(+) create mode 100644 virt/kvm/arm/vgic/vgic-v2-nested.c diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 9c35e9a..8573faf 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -37,3 +37,4 @@ kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o kvm-$(CONFIG_KVM_ARM_NESTED_HYP) += handle_exit_nested.o kvm-$(CONFIG_KVM_ARM_NESTED_HYP) += emulate-nested.o +kvm-$(CONFIG_KVM_ARM_NESTED_HYP) += $(KVM)/arm/vgic/vgic-v2-nested.o diff --git a/virt/kvm/arm/vgic/vgic-v2-nested.c b/virt/kvm/arm/vgic/vgic-v2-nested.c new file mode 100644 index 0000000..b13128e --- /dev/null +++ b/virt/kvm/arm/vgic/vgic-v2-nested.c @@ -0,0 +1,207 @@ +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +static inline struct vgic_v2_cpu_if *vcpu_nested_if(struct kvm_vcpu *vcpu) +{ + return &vcpu->arch.vgic_cpu.nested_vgic_v2; +} + +static inline struct vgic_v2_cpu_if *vcpu_shadow_if(struct kvm_vcpu *vcpu) +{ + return &vcpu->arch.vgic_cpu.shadow_vgic_v2; +} + +static unsigned long vgic_mmio_read_v2_vtr(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + u32 reg; + + reg = kvm_vgic_global_state.nr_lr - 1; + reg |= 0b100 << 26; + reg |= 0b100 << 29; + + return reg; +} + +static inline bool lr_triggers_eoi(u32 lr) +{ + return !(lr & (GICH_LR_STATE | GICH_LR_HW)) && (lr & GICH_LR_EOI); +} + +static unsigned long get_eisr(struct kvm_vcpu *vcpu, bool upper_reg) +{ + struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu); + int max_lr = upper_reg ? 64 : 32; + int min_lr = upper_reg ? 32 : 0; + int nr_lr = min(kvm_vgic_global_state.nr_lr, max_lr); + int i; + u32 reg = 0; + + for (i = min_lr; i < nr_lr; i++) { + if (lr_triggers_eoi(cpu_if->vgic_lr[i])) + reg |= BIT(i - min_lr); + } + + return reg; +} + +static unsigned long vgic_mmio_read_v2_eisr0(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + return get_eisr(vcpu, false); +} + +static unsigned long vgic_mmio_read_v2_eisr1(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + return get_eisr(vcpu, true); +} + +static u32 get_elrsr(struct kvm_vcpu *vcpu, bool upper_reg) +{ + struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu); + int max_lr = upper_reg ? 64 : 32; + int min_lr = upper_reg ? 32 : 0; + int nr_lr = min(kvm_vgic_global_state.nr_lr, max_lr); + u32 reg = 0; + int i; + + for (i = min_lr; i < nr_lr; i++) { + if (!(cpu_if->vgic_lr[i] & GICH_LR_STATE)) + reg |= BIT(i - min_lr); + } + + return reg; +} + +static unsigned long vgic_mmio_read_v2_elrsr0(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + return get_elrsr(vcpu, false); +} + +static unsigned long vgic_mmio_read_v2_elrsr1(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + return get_elrsr(vcpu, true); +} + +static unsigned long vgic_mmio_read_v2_misr(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu); + int nr_lr = kvm_vgic_global_state.nr_lr; + u32 reg = 0; + + if (vgic_mmio_read_v2_eisr0(vcpu, addr, len) || + vgic_mmio_read_v2_eisr1(vcpu, addr, len)) + reg |= GICH_MISR_EOI; + + if (cpu_if->vgic_hcr & GICH_HCR_UIE) { + u32 elrsr0 = vgic_mmio_read_v2_elrsr0(vcpu, addr, len); + u32 elrsr1 = vgic_mmio_read_v2_elrsr1(vcpu, addr, len); + int used_lrs; + + used_lrs = nr_lr - (hweight32(elrsr0) + hweight32(elrsr1)); + if (used_lrs <= 1) + reg |= GICH_MISR_U; + } + + /* TODO: Support remaining bits in this register */ + return reg; +} + +static unsigned long vgic_mmio_read_v2_gich(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu); + u32 value; + + switch (addr & 0xfff) { + case GICH_HCR: + value = cpu_if->vgic_hcr; + break; + case GICH_VMCR: + value = cpu_if->vgic_vmcr; + break; + case GICH_APR: + value = cpu_if->vgic_apr; + break; + case GICH_LR0 ... (GICH_LR0 + 4 * (VGIC_V2_MAX_LRS - 1)): + value = cpu_if->vgic_lr[(addr & 0xff) >> 2]; + break; + default: + return 0; + } + + return value; +} + +static void vgic_mmio_write_v2_gich(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu); + + switch (addr & 0xfff) { + case GICH_HCR: + cpu_if->vgic_hcr = val; + break; + case GICH_VMCR: + cpu_if->vgic_vmcr = val; + break; + case GICH_APR: + cpu_if->vgic_apr = val; + break; + case GICH_LR0 ... (GICH_LR0 + 4 * (VGIC_V2_MAX_LRS - 1)): + cpu_if->vgic_lr[(addr & 0xff) >> 2] = val; + break; + } +} + +static const struct vgic_register_region vgic_v2_gich_registers[] = { + REGISTER_DESC_WITH_LENGTH(GICH_HCR, + vgic_mmio_read_v2_gich, vgic_mmio_write_v2_gich, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_VTR, + vgic_mmio_read_v2_vtr, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_VMCR, + vgic_mmio_read_v2_gich, vgic_mmio_write_v2_gich, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_MISR, + vgic_mmio_read_v2_misr, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_EISR0, + vgic_mmio_read_v2_eisr0, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_EISR1, + vgic_mmio_read_v2_eisr1, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_ELRSR0, + vgic_mmio_read_v2_elrsr0, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_ELRSR1, + vgic_mmio_read_v2_elrsr1, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_APR, + vgic_mmio_read_v2_gich, vgic_mmio_write_v2_gich, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICH_LR0, + vgic_mmio_read_v2_gich, vgic_mmio_write_v2_gich, + 4 * VGIC_V2_MAX_LRS, VGIC_ACCESS_32bit), +};