From patchwork Thu Jun 29 18:06:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 9817621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 867AD60365 for ; Thu, 29 Jun 2017 18:07:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7DA2022376 for ; Thu, 29 Jun 2017 18:07:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 724062878A; Thu, 29 Jun 2017 18:07:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.4 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ECA5E22376 for ; Thu, 29 Jun 2017 18:07:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752729AbdF2SHG (ORCPT ); Thu, 29 Jun 2017 14:07:06 -0400 Received: from foss.arm.com ([217.140.101.70]:59408 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752640AbdF2SHE (ORCPT ); Thu, 29 Jun 2017 14:07:04 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0687C80D; Thu, 29 Jun 2017 11:06:54 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (e107155-lin.cambridge.arm.com [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AEC553F4FF; Thu, 29 Jun 2017 11:06:52 -0700 (PDT) From: Sudeep Holla To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Christoffer Dall , Marc Zyngier Subject: [PATCH] arm64: kvm: reuse existing cache type/info related macros Date: Thu, 29 Jun 2017 19:06:44 +0100 Message-Id: <1498759604-7564-1-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We already have various macros related to cache type and bitfields in CLIDR system register. We can replace some of the hardcoded values here using those existing macros. This patch reuses those existing cache type/info related macros and replaces the hardcorded values. It also removes some of the comments that become trivial with the macro names. Cc: Catalin Marinas Cc: Will Deacon Cc: Christoffer Dall Cc: Marc Zyngier Signed-off-by: Sudeep Holla --- arch/arm64/include/asm/cache.h | 7 +++++++ arch/arm64/kernel/cacheinfo.c | 7 ------- arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++-------------- 3 files changed, 22 insertions(+), 21 deletions(-) Hi, I dropped the support for 64bit format CCSIDR after Will's commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing"). However I forgot to follow up on this patch which can be still applied. So just reposting it. Regards, Sudeep diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index ea9bb4e0e9bb..70fd4357ed38 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -49,6 +49,13 @@ #define ICACHEF_VPIPT 1 extern unsigned long __icache_flags; +#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + /* * Whilst the D-side always behaves as PIPT on AArch64, aliasing is * permitted in the I-cache. diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 380f2e2fbed5..4798aa4bc17b 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -20,13 +20,6 @@ #include #include -#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ -#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) -#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) -#define CLIDR_CTYPE(clidr, level) \ - (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) - static inline enum cache_type get_cache_type(int level) { u64 clidr; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0fe27024a2e1..e4107047f405 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -21,11 +21,13 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -68,7 +70,7 @@ static bool read_from_write_only(struct kvm_vcpu *vcpu, static u32 cache_levels; /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ -#define CSSELR_MAX 12 +#define CSSELR_MAX ((MAX_CACHE_LEVEL - 1) << 1) /* Which cache CCSIDR represents depends on CSSELR value. */ static u32 get_ccsidr(u32 csselr) @@ -1894,19 +1896,18 @@ static bool is_valid_cache(u32 val) return false; /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level = (val >> 1); - ctype = (cache_levels >> (level * 3)) & 7; + level = (val >> 1) + 1; + ctype = CLIDR_CTYPE(cache_levels, level); switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ + case CACHE_TYPE_INST: + return (val & CACHE_TYPE_INST); + case CACHE_TYPE_DATA: + case CACHE_TYPE_UNIFIED: + return !(val & CACHE_TYPE_INST); + case CACHE_TYPE_SEPARATE: return true; + case CACHE_TYPE_NOCACHE: default: /* Reserved: we can't know instruction or data. */ return false; } @@ -2173,11 +2174,11 @@ void kvm_sys_reg_table_init(void) */ get_clidr_el1(NULL, &clidr); /* Ugly... */ cache_levels = clidr.val; - for (i = 0; i < 7; i++) - if (((cache_levels >> (i*3)) & 7) == 0) + for (i = 1; i <= MAX_CACHE_LEVEL; i++) + if (CLIDR_CTYPE(cache_levels, i) == CACHE_TYPE_NOCACHE) break; /* Clear all higher bits. */ - cache_levels &= (1 << (i*3))-1; + cache_levels &= (1 << CLIDR_CTYPE_SHIFT(i)) - 1; } /**