From patchwork Tue Oct 3 03:11:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 9981457 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BB70D60384 for ; Tue, 3 Oct 2017 03:12:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE21F2881D for ; Tue, 3 Oct 2017 03:12:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A2D3428822; Tue, 3 Oct 2017 03:12:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC9F42881D for ; Tue, 3 Oct 2017 03:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752024AbdJCDMN (ORCPT ); Mon, 2 Oct 2017 23:12:13 -0400 Received: from mail-it0-f46.google.com ([209.85.214.46]:48272 "EHLO mail-it0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751953AbdJCDL7 (ORCPT ); Mon, 2 Oct 2017 23:11:59 -0400 Received: by mail-it0-f46.google.com with SMTP id m123so10018788ita.3 for ; Mon, 02 Oct 2017 20:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=shAXUEFqjkM2YlH2GE/P3dGN4TcJhI5ThHwGLeIdR+c=; b=FmA+OHsMcQs+Paivfd1ki98uBzoX27jQhiL07euIyfcJok3CJj5c0HdRTRgnLjhKqK ktPGcFgL1Kw0PIjrUBOqeZ6+yN1dJ/rYOofV1sAKeywCRHNi5VKK/ZwO2Puqanj125EC Z3dEJ5RDIIC7SrL+A6NiC1Prw4NdSfZJFfx4A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=shAXUEFqjkM2YlH2GE/P3dGN4TcJhI5ThHwGLeIdR+c=; b=GvKpb5v8A/eXUoQOQjs57mYonUfUgaXeUDcasvOj+/FMU9c95s67eJcyMehurv7zMy /gV8HcmUvuDI3IXyTqk/00Yh0Ou1npyS6BL1gROPvCMo9RWs/RxYMKZXFHIAd2er5wmK 0bTWJ3Sd58Ao6ixIkqobIqnUfqbmifqUo2PgzDRwnV0+PC5/wcM1KWsw7cUpMZ0iWnd/ UmC9ZZAqmLyQivXoP4QUlejVtbHX1T57YAexBoHvjtOA5Dn4ATyaPAPTVb/LvBO16DfD 8b4i8qhk0OPbx0lRLmqqaNDnn6ibXqTKw/+2hqGOfgiBCNj7no+Pk1lPMx5XTtb95lKW J9Sg== X-Gm-Message-State: AHPjjUgZCip5pT8/BE5ZS0nrMm1atOC8qKCXpZXFNe0//roPqt/XDR0w I+Dh08kx1QGqlLzea/Kjg+UR3w== X-Google-Smtp-Source: AOwi7QAgT2hZ59eOGT2UYA1spZn9v3uX37s1EggY7gfR4/meF0PLT+zUc4SVMpeo99xM85j9SZXGEg== X-Received: by 10.36.39.142 with SMTP id g136mr23679752ita.73.1507000318531; Mon, 02 Oct 2017 20:11:58 -0700 (PDT) Received: from node.jintackl-qv28633.kvmarm-pg0.wisc.cloudlab.us (c220g1-031126.wisc.cloudlab.us. [128.104.222.76]) by smtp.gmail.com with ESMTPSA id h84sm5367193iod.72.2017.10.02.20.11.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Oct 2017 20:11:57 -0700 (PDT) From: Jintack Lim To: christoffer.dall@linaro.org, marc.zyngier@arm.com, kvmarm@lists.cs.columbia.edu Cc: jintack@cs.columbia.edu, pbonzini@redhat.com, rkrcmar@redhat.com, catalin.marinas@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jintack Lim Subject: [RFC PATCH v2 18/31] KVM: arm64: Enumerate AT and TLBI instructions to emulate Date: Mon, 2 Oct 2017 22:11:00 -0500 Message-Id: <1507000273-3735-16-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507000273-3735-1-git-send-email-jintack.lim@linaro.org> References: <1507000273-3735-1-git-send-email-jintack.lim@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP List all system instructions to emulate. This patch only introduces the definitions, emulation handlers will be added in subsequent patches. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/sysreg.h | 38 ++++++++++++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 26 ++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a051d42..53df733 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -367,6 +367,44 @@ #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) +/* AT instructions */ +#define AT_Op0 1 +#define AT_CRn 7 + +#define AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0) +#define AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1) +#define AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2) +#define AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3) +#define AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0) +#define AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1) +#define AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0) +#define AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1) +#define AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4) +#define AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5) +#define AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6) +#define AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7) + +/* TLBI instructions */ +#define TLBI_Op0 1 +#define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */ +#define TLBI_CRn 8 +#define tlbi_insn_el2(CRm, Op2) sys_insn(TLBI_Op0, TLBI_Op1_EL2, TLBI_CRn, (CRm), (Op2)) + +#define TLBI_IPAS2E1IS tlbi_insn_el2(0, 1) +#define TLBI_IPAS2LE1IS tlbi_insn_el2(0, 5) +#define TLBI_ALLE2IS tlbi_insn_el2(3, 0) +#define TLBI_VAE2IS tlbi_insn_el2(3, 1) +#define TLBI_ALLE1IS tlbi_insn_el2(3, 4) +#define TLBI_VALE2IS tlbi_insn_el2(3, 5) +#define TLBI_VMALLS12E1IS tlbi_insn_el2(3, 6) +#define TLBI_IPAS2E1 tlbi_insn_el2(4, 1) +#define TLBI_IPAS2LE1 tlbi_insn_el2(4, 5) +#define TLBI_ALLE2 tlbi_insn_el2(7, 0) +#define TLBI_VAE2 tlbi_insn_el2(7, 1) +#define TLBI_ALLE1 tlbi_insn_el2(7, 4) +#define TLBI_VALE2 tlbi_insn_el2(7, 5) +#define TLBI_VMALLS12E1 tlbi_insn_el2(7, 6) + /* Common SCTLR_ELx flags. */ #define SCTLR_ELx_EE (1 << 25) #define SCTLR_ELx_I (1 << 12) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 481bea64..8d04926 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1624,6 +1624,32 @@ static bool access_id_aa64mmfr0_el1(struct kvm_vcpu *v, #define SYS_INSN_TO_DESC(insn, access_fn, forward_fn) \ { SYS_DESC((insn)), (access_fn), NULL, 0, 0, NULL, NULL, (forward_fn) } static struct sys_reg_desc sys_insn_descs[] = { + SYS_INSN_TO_DESC(AT_S1E1R, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E1W, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E0R, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E0W, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E1RP, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E1WP, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E2R, NULL, NULL), + SYS_INSN_TO_DESC(AT_S1E2W, NULL, NULL), + SYS_INSN_TO_DESC(AT_S12E1R, NULL, NULL), + SYS_INSN_TO_DESC(AT_S12E1W, NULL, NULL), + SYS_INSN_TO_DESC(AT_S12E0R, NULL, NULL), + SYS_INSN_TO_DESC(AT_S12E0W, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_IPAS2E1IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_IPAS2LE1IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_ALLE2IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_VAE2IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_ALLE1IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_VALE2IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_VMALLS12E1IS, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_IPAS2E1, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_IPAS2LE1, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_ALLE2, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_VAE2, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_ALLE1, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_VALE2, NULL, NULL), + SYS_INSN_TO_DESC(TLBI_VMALLS12E1, NULL, NULL), }; #define reg_to_match_value(x) \