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[128.104.222.76]) by smtp.gmail.com with ESMTPSA id h84sm5367193iod.72.2017.10.02.20.11.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Oct 2017 20:11:44 -0700 (PDT) From: Jintack Lim To: christoffer.dall@linaro.org, marc.zyngier@arm.com, kvmarm@lists.cs.columbia.edu Cc: jintack@cs.columbia.edu, pbonzini@redhat.com, rkrcmar@redhat.com, catalin.marinas@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 07/31] KVM: arm64: Setup vttbr_el2 on each VM entry Date: Mon, 2 Oct 2017 22:10:49 -0500 Message-Id: <1507000273-3735-5-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507000273-3735-1-git-send-email-jintack.lim@linaro.org> References: <1507000273-3735-1-git-send-email-jintack.lim@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Christoffer Dall Now that the vttbr value will be different depending on the VM's exception level, we set it on each VM entry. We only have one mmu instance at this point, but there will be multiple of them if we come to run nested VMs. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim --- arch/arm64/kvm/context.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index a7811e1..afd1702 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -18,6 +18,7 @@ #include #include #include +#include struct el1_el2_map { enum vcpu_sysreg el1; @@ -174,6 +175,15 @@ static void flush_shadow_el1_sysregs(struct kvm_vcpu *vcpu) flush_shadow_el1_sysregs_nvhe(vcpu); } +static void setup_s2_mmu(struct kvm_vcpu *vcpu) +{ + struct kvm_s2_mmu *mmu = &vcpu->kvm->arch.mmu; + struct kvm_s2_vmid *vmid = vcpu_get_active_vmid(vcpu); + + vcpu->arch.hw_vttbr = kvm_get_vttbr(vmid, mmu); + vcpu->arch.hw_mmu = mmu; +} + /* * List of EL0 and EL1 registers which we allow the virtual EL2 mode to access * directly without trapping. This is possible because the impact of @@ -323,6 +333,8 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) setup_mpidr_el1(vcpu); ctxt->hw_sys_regs = ctxt->sys_regs; } + + setup_s2_mmu(vcpu); } /**